Table of Contents
Advances in Electronics
Volume 2015, Article ID 713843, 13 pages
http://dx.doi.org/10.1155/2015/713843
Research Article

FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

1Department of PG Studies in Engineering, S. A. Engineering College (Affiliated to Anna University), Poonamallee-Avadi Road, Veeraraghavapuram, Chennai, Tamil Nadu 600 077, India
2Department of Computer Science and Engineering, S. A. Engineering College (Affiliated to Anna University), Poonamallee-Avadi Road, Veeraraghavapuram, Chennai, Tamil Nadu 600 077, India

Received 30 September 2014; Revised 21 April 2015; Accepted 4 May 2015

Academic Editor: Gianluca Traversi

Copyright © 2015 V. Kokilavani et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work, two new hybrid carry select adders are proposed involving the carry select and section-carry based carry lookahead subadders with/without binary to excess 1 converters. Seven different carry select adders were implemented in Verilog HDL and their performances were analyzed under two scenarios, dual-operand addition and multioperand addition, where individual operands are of sizes 32 and 64-bits. In the case of dual-operand additions, the hybrid carry select adder comprising the proposed carry select and section-carry based carry lookahead configurations is the fastest. With respect to multioperand additions, the hybrid carry select adder containing the carry select and conventional carry lookahead or section-carry based carry lookahead structures produce similar optimized performance.