Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2&#x2009;:&#x2009;1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2&#x2009;:&#x2009;1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work, two new hybrid carry select adders are proposed involving the carry select and section-carry based carry lookahead subadders with/without binary to excess 1 converters. Seven different carry select adders were implemented in Verilog HDL and their performances were analyzed under two scenarios, dual-operand addition and multioperand addition, where individual operands are of sizes 32 and 64-bits. In the case of dual-operand additions, the hybrid carry select adder comprising the proposed carry select and section-carry based carry lookahead configurations is the fastest. With respect to multioperand additions, the hybrid carry select adder containing the carry select and conventional carry lookahead or section-carry based carry lookahead structures produce similar optimized performance.

V. Kokilavani

K. Preethi

P. Balasubramanian

FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

Previously, authors have proposed CPLAG and MCPLAG circuits extracting benefits of CPL family implemented based upon semiadiabatic logic for low power VLSI circuit design along with gating concept. Also authors have communicated RCPLAG circuits adding another dimension of reconfigurability into CPLAG/MCPLAG circuits. Moving ahead, in this paper, authors have implemented/reconfigured RCPLAG universal Nand/And gate and universal Nor/Or gate for extracting behavior of dynamic positive edge triggered DFF. Authors have also implemented Adder/Subtractor circuit using different techniques. Authors have also reported modification in PFAL semiadiabatic circuit family to further reduce the power dissipation. Functionality of these is verified and found to be satisfactory. Further these are examined rigorously with voltage, <svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" style="vertical-align:-3.408751pt" id="M1" height="12.4067pt" version="1.1" viewBox="-0.0498162 -8.99795 26.1298 12.4067" width="26.1298pt"><g transform="matrix(.0135,0,0,-0.0135,0,0)"><path id="g113-68" d="M645 631C614 643 545 666 457 666C215 666 23 519 23 283C23 90 158 -16 337 -16C412 -16 489 2 522 10C543 39 590 127 606 167L580 181C519 89 459 18 348 18C201 18 122 136 122 287C122 464 244 632 435 632C544 632 602 595 608 472L639 475C643 526 645 581 645 631Z"/></g><g transform="matrix(.0095,0,0,-0.0095,8.982,3.264)"><path id="g190-109" d="M238 0V26C174 32 166 38 166 104V712C132 700 70 683 18 677V653C81 647 87 645 87 577V104C87 38 78 32 15 26V0H238Z"/></g><g transform="matrix(.0095,0,0,-0.0095,11.382,3.264)"><path id="g190-112" d="M257 449C165 449 37 374 37 209C37 98 119 -12 256 -12C355 -12 473 65 473 226C473 349 381 449 257 449ZM244 416C333 416 380 320 380 204C380 67 329 21 267 21C184 21 130 115 130 241C130 354 184 416 244 416Z"/></g><g transform="matrix(.0095,0,0,-0.0095,16.266,3.264)"><path id="g190-98" d="M433 39L423 65C413 59 399 54 387 54C370 54 352 69 352 114V299C352 352 342 392 307 422C285 440 255 449 225 449C168 437 102 399 75 379C56 365 44 353 44 339C44 315 69 296 87 296C101 296 111 303 116 319C124 349 133 371 145 385C156 397 171 404 190 404C241 404 275 364 275 291V274C253 256 180 229 120 209C65 190 39 159 39 110C39 47 88 -12 159 -12C189 -12 237 25 277 52C282 35 288 21 301 8C312 -3 333 -12 348 -12L433 39ZM275 84C256 65 221 48 195 48C164 48 124 73 124 124C124 161 146 180 185 198C206 208 254 229 275 240V84Z"/></g><g transform="matrix(.0095,0,0,-0.0095,20.429,3.264)"><path id="g190-101" d="M517 51L485 54C448 58 441 63 441 115V712C404 700 337 684 285 678V653C357 648 362 645 362 580V437C339 446 309 449 295 449C159 449 38 340 38 201C38 61 143 -12 223 -12C234 -12 261 -6 301 17L362 53V-12C420 9 495 22 517 26V51ZM362 85C338 67 301 51 266 51C201 51 128 109 128 228C128 373 212 411 259 411C296 411 338 395 362 360V85Z"/></g></svg>, temperature, and transistor size variation. Performance of these is examined with these variations with power dissipation, delays, rise, and fall times associated. From the analysis it is found that best operating condition for DFF based upon RCPLAG universal gate can be achieved at supply voltage lower than 3&#x2009;V which can be used for different transistor size up to 36&#x2009;<i>&#x3bc;</i>m. Average power dissipation is 0.2&#x2009;<i>&#x3bc;</i>W at 1&#x2009;V and 30&#x2009;<i>&#x3bc;</i>W at 2&#x2009;V at 100&#x2009;ff <svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" style="vertical-align:-3.408751pt" id="M2" height="12.4067pt" version="1.1" viewBox="-0.0498162 -8.99795 26.1298 12.4067" width="26.1298pt"><g transform="matrix(.0135,0,0,-0.0135,0,0)"><use xlink:href="#g113-68"/></g><g transform="matrix(.0095,0,0,-0.0095,8.982,3.264)"><use xlink:href="#g190-109"/></g><g transform="matrix(.0095,0,0,-0.0095,11.382,3.264)"><use xlink:href="#g190-112"/></g><g transform="matrix(.0095,0,0,-0.0095,16.266,3.264)"><use xlink:href="#g190-98"/></g><g transform="matrix(.0095,0,0,-0.0095,20.429,3.264)"><use xlink:href="#g190-101"/></g></svg> 25&#xb0;C approximately. Average power dissipated by CPLAG Adder/Subtractot is 58&#x2009;<i>&#x3bc;</i>W. Modified PFAL circuit reduces average power by 9&#x25; approximately.

Manoj Sharma

Arti Noor

Reconfigurable CPLAG and Modified PFAL Adiabatic  Logic Circuits

A new proposed compensation driver circuit of flat-panel display (FPD) based on organic light emitting diodes (OLEDs) and on poly-crystalline silicon thin-film transistors (poly-Si TFTs) is presented. This driver circuit is developed for an active-matrix organic light-emitting-diode (AMOLED) display and its efficiency is verified compared with the conventional configuration with 2 TFTs. According to results, this circuit is suitable to achieve acceptable level for power consumption, high contrast, maximum gray levels, and better brightness. And, to show this, a stable driving scheme is developed for circuit with much compensation such as against the data degradation, the threshold voltage dispersions of TFT drive, and suppression of TFT leakage current effect.

Said Saad

Lotfi Hassine

High Efficiency Driver for AMOLED with Compensation

This paper presents multiphase sinusoidal oscillators (MSOs) using operational transresistance amplifier (OTRA) based all pass networks. Both even and odd phase oscillations of equal amplitudes which are equally spaced in phase can be produced using single all pass section per phase. The proposed MSOs provide voltage output and can readily be used for driving voltage input circuits without increasing component count. The effect of nonideality of OTRA on the circuit performance is also analysed. The functionality of the proposed circuit is verified through PSPICE simulations.

Rajeshwari Pandey

Neeta Pandey

Romita Mullick

Sarjana Yadav

Rashika Anurag

All Pass Network Based MSO Using OTRA

Advances in Electronics

Retracted: Occluded Face Recognition Based on Double Layers Module Sparsity Difference

A wearable smart locator band is an electronic device which can be worn on the wrist of the children to monitor and keep an eye on them. As the number of mishaps with children is increasing, it is a must to keep them safe. This also helps reducing crime rates. The research study proposed the development of a wearable smart locator band that helps keeping track of kids. The developed device includes an AVR microcontroller (ATmega8515), global positioning system (GPS), global system for mobile (GSM), and switching unit and the monitoring unit includes Android mobile device in parent&#x2019;s hand with web based Android application as well as location indicated on a Google Map. This development is very useful for senior people and individuals suffering from memory diseases. This device, hence, behaves as a communication interface between wearer and caregiver.

Isha Goel

Dilip Kumar

Design and Implementation of Android Based Wearable Smart Locator Band for People with Autism, Dementia, and Alzheimer

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Advances in Electronics