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Advances in Fuzzy Systems
Volume 2014, Article ID 841976, 10 pages
Research Article

Designing of 2-Stage CPU Scheduler Using Vague Logic

1Department of Computer Science & Engineering, ITM University, Gurgaon, India
2Department of Computer Science, University of Kota, Rajasthan, India
3Alpha Global IT, Toronto, ON, Canada

Received 15 January 2014; Revised 29 April 2014; Accepted 25 June 2014; Published 22 July 2014

Academic Editor: Adel M. Alimi

Copyright © 2014 Supriya Raheja et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Supriya Raheja, Reena Dhadich, and Smita Rajpal, “Designing of 2-Stage CPU Scheduler Using Vague Logic,” Advances in Fuzzy Systems, vol. 2014, Article ID 841976, 10 pages, 2014.