Designing of 2-Stage CPU Scheduler Using Vague Logic

Table 3

Outcomes of Task Set 1.

S. no.	Scheduling technique	𝑊𝑠 (ns)	𝑇𝑠 (ns)	𝑁𝑠 (ns)
1	PS	22	32	3.99
2	SJF	11	21	1.92
3	FS	12	22	3.99
4	VOPS	11	21	1.92