Designing of Vague Logic Based 2-Layered Framework for CPU Scheduler

Figure 10

(a) Waiting time (Sample Task Set). (b) Turnaround time (Sample Task Set). (c) Response time (Sample Task Set). (d) Normalized turnaround time (Sample Task Set). (e) Context switches (Sample Task Set). (f) Overall performance (Sample Task Set).

(a)

(b)

(c)

(d)

(e)

(f)