Resistance Switching Characteristics in ZnO-Based Nonvolatile Memory Devices
Bipolar resistance switching characteristics are demonstrated in Pt/ZnO/Pt nonvolatile memory devices. A negative differential resistance or snapback characteristic can be observed when the memory device switches from a high resistance state to a low resistance state due to the formation of filamentary conducting path. The dependence of pulse width and temperature on set/reset voltages was examined in this work. The exponentially decreasing trend of set/reset voltage with increasing pulse width is observed except when pulse width is larger than 1 s. Hence, to switch the ZnO memory devices, a minimum set/reset voltage is required. The set voltage decreases linearly with the temperature whereas the reset voltage is nearly temperature-independent. In addition, the ac cycling endurance can be over 106 switching cycles, whereas, the dependence of HRS/LRS resistance distribution indicates that a significant memory window closure may take place after about 102 dc switching cycles.
Developments of next generation nonvolatile memory (NVM) devices are required because the physical limitations of traditional Flash memory devices are approaching. In recent years, the resistance random access memory (RRAM) device has attracted a great deal of attention for the next generation NVM applications . Since the RRAM technology is well compatible with the complimentary metal oxide semiconductor (CMOS) process , the scaling of RRAM devices may keep on in terms of the low power operation. This benefit will bring a strong cost-competitiveness to RRAM. In addition, the advantages of RRAM include small cell size, simple cell structure, high switching speed, high operation durability, multi state switching, and three-dimensional architecture [1–5]. The resistance switching behavior has been reported for a variety of materials such as perovskite-type oxides [1, 3], binary metal oxides [2–4], solid-state electrolytes , organic compounds , and amorphous Si . In these RRAM materials being studied, binary metal oxides are most potential due to their simple constituents, good compatibility with CMOS processes, and resistive nature to thermal/chemical damages [2, 4, 8].
In this work, Pt/ZnO/Pt capacitors were fabricated and investigated for the NVM applications. The dependence of pulse width and temperature on set/reset voltages was examined. Experimental results show that a minimum set/reset voltage is required to switch the ZnO memory devices. The exponential decreasing trend of set/reset voltage with increasing pulse width is observed except when pulse width is larger than 1 s. The set voltage decreases linearly with the temperature, whereas the reset voltage is almost temperature independent. In addition, the resistance values both at high resistance state (HRS) and low resistance state (LRS) in different Pt/ZnO/Pt memory devices were characterized. The dependence of HRS/LRS resistance distribution on set/reset switching cycles indicates that the memory window begins to close after about 100 voltage sweeping cycles. Although the dc cycling endurance is detrimental, the ac cycling endurance over 106 switching cycles can be achieved.
In this work, the sample structure of the resistive switching memory devices is metal insulator metal (MIM) capacitor, as indicated in Figure 1. The ZnO film was deposited on Pt/Ti/SiO2/Si substrates by rf magnetron sputtering at room temperature. The ZnO film thickness is 25 nm. The sputtering power is 40 W. The working pressure is 5 × 10−3 Torr in Ar ambient with a flow rate of 25 sccm. Pt top electrode was then defined by rf magnetron sputtering through a metal shadow mask. The electrical properties of the fabricated Pt/ZnO/Pt memory devices were characterized under dark condition by using Agilent 4156C semiconductor parameter analyzer and Agilent 8110A pulse pattern generator, as well as Barth 4002 transmission line pulse generator. During the electrical characterizations, the bias voltage (or current) was applied on the top electrode with the bottom electrode grounded.
3. Results and Discussion
In this work, an initial forming process is required to achieve the bipolar resistance switching behavior on the virgin memory cells. Typicalswitching characteristics in the Pt/ZnO/Pt memory devices are shown in Figure 2. The forming voltage is about 4 V. After the forming process, the memory device is in low resistance state (LRS). By sweeping the voltage in negative side without a current compliance (), the device current decreases suddenly at a reset voltage () or a reset current (), and the device is switched from an LRS to an HRS. This event is defined as the reset process. Then applying the voltage in positive side, an abrupt increase of the device current takes place at a set voltage () or a set current (). Thetriggers the memory cell from an HRS to an LRS, which is defined as the SET process. Obviously, the V should be larger than V, and theA should be smaller than the A . Since the resistance switching depends on the polarity of applied voltage, the resistance switching in Pt/ZnO/Pt structure is bipolar. The bipolar resistance switching is also found in doped ZnO films with sulfur, cobalt, or manganese [9, 10] and in the structure of TiN/ZnO/Pt . In addition, the unipolar resistance switching can be observed in the structures of Al/ZnO/Al  and Cu/ZnO/n+-Si . Even both unipolar and bipolar resistance switchings may coexist in the structure of Ag/ZnO/Pt . The voltage-biased set process results in a sudden current jump at, which causes the memory cell to switch from an HRS to an LRS. If, however, the set process is performed by the current sweeping, a negative differential resistance or snapback characteristic may be observed . When the memory cell is switched from an HRS to an LRS at(or), the current transports through quite low resistance immediately due to the conductive filaments formed between two electrodes and then the voltage across the memory cell begins to decrease significantly resulting in thesnapback characteristic (indicated by) as shown in Figure 3. Accordingly, the current-biased setcurve is much different from the voltage-biased one after the onset of resistance switching from an HRS to an LRS, because the voltage will continue to increase during the voltage sweep mode (indicated by). Note that thesnapback phenomena can be often observed in the electrostatic discharge (ESD) protection devices  and even in ultrathin SiO2 films . Since the electric-pulse-induced resistance switching could be significantly affected by the ac voltage pulse width (), the relationship between set/reset switching voltage andwas examined. In this work, bothanddecrease with increasing. An exponential relationship between/andcan be observed for the condition of low(10−7 to 100 s), as shown in Figure 3. Meanwhile, a critical threshold voltage is approached for large(>1 s) . This implies that a minimum set/reset voltage is required to switch the ZnO memory devices. The thresholdsandare about 0.55 V and −0.25 V, respectively.
Figure 4 shows the temperature dependence ofcharacteristics both in HRS and LRS. Experimental results show that the device current increases with increasing temperature both in HRS and LRS. According to the temperature dependence ofcharacteristics , the conduction mechanism in Pt/ZnO/Pt structure is dominated by the hopping conduction in HRS. The hopping conduction is not the electrode-limited conduction mechanism but the bulk-limited conduction mechanism . The electrode-limited conduction mechanism depends on the electrical properties at the electrode-dielectric contact. However, the bulk-limited conduction mechanism depends only on the properties of the dielectric itself. This may imply that the resistance switching mechanism in Pt/ZnO/Pt structure is not the interface type but the filament type. In addition, the device current is enhanced at the elevated temperature in HRS. Consequently, the switching voltage is lowered by the energy requirement of conductive filament formation. Due to the thermally assisted current conduction, the set voltage decreases with increasing temperature. Figure 5 shows that the set voltage decreases linearly with the temperature, whereas the reset voltage is almost temperature independent. The constant reset voltage is also observed during the dc cycling endurance tests performed by voltage-biased set/reset switching for the Pt/ZnO/Pt memory devices. Figure 6 shows thecurves before and after the test of dc cycling endurance performed by voltage sweepings at room temperature. The reset voltage during the test of dc cycling endurance keeps approximately constant. The uniformvalue suggests that the dominant reset process may result from the same rupture place in the conducting filamentary paths  leading to the dramatic current drop between both electrodes. Note that theof 3 mA was set to prevent the permanent breakdown of the memory devices during the set processes. On the contrary, nowas set for the reset process. As shown in Figure 6, the HRS/LRS resistance ratio is on the order of 102−103 before the test of dc cycling endurance. Whereas the current in HRS increases after about 100 dc voltage sweeping cycles, which results in the change of HRS/LRS resistance ratio. Figure 7 shows the Weibull cumulative distributions of HRS/LRS resistance (/RLRS) values versus the cycle numbers of dc switching endurances for different Pt/ZnO/Pt memory devices. The Weibull distribution function is frequently used in semiconductor failure analysis and can be expressed as  whereis the cumulative distribution function of failure,is the resistance value either in HRS or LRS,is the HRS/LRS resistance value at approximately 63rd percentile, andis the Weibull shape factor, often called Weibull slope. Usually,is plotted as a function ofand this will yield a straight line. In this work, the Weibull slope () was estimated by the method of maximum likelihood estimation . Thevalues for memory devices in LRS are very large, which means that the LRS resistance () values are extremely centered. As the dc switching cycles increase, thenearly keeps constant even thoughincreases slightly with the switching cycle. Meanwhile, thevalues for memory devices in HRS are much smaller than those in LRS. This means that the HRS resistances () have a relatively broad distribution. In addition, thevalues begin to increase significantly after 100 dc switching cycles, as indicated in Figure 7. Therefore, the memory window begins to close after about 100 voltage-biased switching cycles. As indicated in Figure 8, the memory window between HRS and LRS is a function of the number of switching cycles. The dc cycling endurance is very detrimental, whereas the ac cycling endurance over 106 switching cycles can be achieved. In the case of dc cycling endurance, the dc forward sweeping voltage may set the memory device into the soft breakdown mode in which the dielectric is stressed by a large compliance current (3 mA). This high stress may result in the dielectric degradation and therefore memory window closing. As the test of ac cycling endurance, the switching between HRS and LRS is highly controlled, reversible, and reproducible. The memory window shows no degradation after 106 ac switching cycles, as shown in Figure 8. In this work, the alternate ac voltage pulses of +1 V and −1 V were applied per 10 ms in the test of ac cycling endurance. The relatively large pulse width (10 ms) was used for worse case. Experimental results showed that ac endurance could be at least higher than 106 switching cycles. This implies that the ZnO thin film is very potential in future nanoscale nonvolatile memory applications. Based on the cycling endurance tests, the serious reliability issue in the dc type is highlighted.
In summary, bipolar resistance switching characteristic was revealed in Pt/ZnO/Pt memory devices. The dependence of pulse width on set/reset voltages indicates that a minimum set/reset voltage is required to switch the memory cells. The set voltage decreases linearly with the temperature, whereas the reset voltage is nearly temperature independent. The dependence of HRS/LRS resistance distribution shows that the memory window closure may occur after about 100 dc switching cycles. The ac cycling endurance shows that no degradation is observed after 106 cycles, which is potential in future nanoscale nonvolatile memory applications.
Conflict of Interests
The author declares that there is no conflict of interests regarding the publication of this paper.
The author thanks the National Science Council, Taiwan, for supporting this work under Contract no. NSC 102-2221-E-130-015-MY2. He also thanks Mr. Peng-Wei Li and Dr. Wen-Yuan Chang for the technical assistance.
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