Charge-Trapping Devices Using Multilayered Dielectrics for Nonvolatile Memory Applications

<table><svg height="18.3125" id="M13" style="vertical-align:-5.73161pt" version="1.1" viewbox="0 0 48.012501 18.3125" width="48.012501" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,11.113)"><path d="M414 650l-6 -28q-63 -4 -78.5 -17.5t-27.5 -71.5l-77 -416q-11 -58 0.5 -71.5t77.5 -17.5l-5 -28h-275l8 28q63 4 79.5 18.5t27.5 70.5l80 416q11 57 -2 71t-81 18l6 28h273z" id="x1D43C"></path></g>
<g transform="matrix(.012,-0,0,-.012,7.487,15.188)"><path d="M517 51v-25q-101 -18 -155 -38v65l-61 -36q-50 -29 -78 -29q-68 0 -126.5 58t-58.5 155q0 103 77 175.5t180 72.5q36 0 67 -12v143q0 48 -11.5 58.5t-65.5 14.5v25q79 9 156 34v-597q0 -38 7.5 -48t36.5 -13zM362 85v275q-35 51 -103 51q-20 0 -40.5 -8.5t-42 -28
t-35 -57.5t-13.5 -89q0 -83 42 -130t96 -47q51 0 96 34z" id="x64"></path></g><g transform="matrix(.012,-0,0,-.012,13.746,15.188)"><path d="M319 325l-25 -7q-33 99 -103 99q-29 0 -47 -19.5t-18 -49.5t22 -49.5t62 -36.5q63 -26 95 -57t32 -79q0 -64 -50 -101t-115 -37q-35 0 -67.5 10.5t-46.5 23.5q-5 11 -11 51t-6 67l27 5q14 -53 46.5 -88.5t75.5 -35.5q29 0 50 19.5t21 50.5t-19.5 51.5t-59.5 39.5
q-28 12 -46 22.5t-38.5 27t-30.5 38.5t-10 49q0 54 42.5 92t109.5 38q48 0 88 -18q6 -15 13 -50.5t9 -55.5z" id="x73"></path></g>
<g transform="matrix(.017,-0,0,-.017,18.725,11.113)"><path d="M300 253l-14 -55h-229l14 55h229z" id="x2D"></path></g><g transform="matrix(.017,-0,0,-.017,24.777,11.113)"><path d="M730 650l-8 -28q-52 -4 -72 -18t-64 -77q-79 -113 -321 -539h-33l-119 541q-13 59 -29.5 73t-66.5 20l7 28h245l-8 -28l-28 -5q-33 -6 -40.5 -15.5t-0.5 -38.5l102 -450h2q191 320 246 430q21 42 15.5 56t-43.5 19l-31 4l7 28h240z" id="x1D449"></path></g>
<g transform="matrix(.012,-0,0,-.012,37.387,15.188)"><path d="M463 437l5 -8q-21 -38 -45 -51l-57 3q30 -35 30 -88q0 -76 -52.5 -118t-122.5 -42q-24 0 -51 5q-30 -21 -30 -42q0 -16 16 -27t47 -11q19 0 54 0.5t52 0.5q36 0 65.5 -8t53.5 -36t24 -74q0 -77 -75 -137.5t-174 -60.5q-79 0 -126 37.5t-48 84.5q0 32 24 56q21 21 83 70
q-49 15 -74 55q-13 20 -11 42q56 21 88 61q-37 16 -62.5 51t-25.5 83q0 78 56.5 122t122.5 44h1q51 0 96 -27q71 4 136 15zM219 418q-34 0 -58 -32t-24 -87q0 -59 26.5 -96.5t67.5 -37.5q35 1 59 32t24 87q0 59 -26 96.5t-69 37.5zM241 -11q-62 0 -87 -21q-46 -39 -46 -78
q0 -41 38 -68.5t94 -27.5q69 0 106.5 31t37.5 80q0 52 -45 71q-33 13 -98 13z" id="x67"></path></g><g transform="matrix(.012,-0,0,-.012,42.956,15.188)"><path d="M319 325l-25 -7q-33 99 -103 99q-29 0 -47 -19.5t-18 -49.5t22 -49.5t62 -36.5q63 -26 95 -57t32 -79q0 -64 -50 -101t-115 -37q-35 0 -67.5 10.5t-46.5 23.5q-5 11 -11 51t-6 67l27 5q14 -53 46.5 -88.5t75.5 -35.5q29 0 50 19.5t21 50.5t-19.5 51.5t-59.5 39.5
q-28 12 -46 22.5t-38.5 27t-30.5 38.5t-10 49q0 54 42.5 92t109.5 38q48 0 88 -18q6 -15 13 -50.5t9 -55.5z" id="x73"></path></g>
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Advances in Materials Science and Engineering

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Figure 2

Figure 2: Charge-Trapping Devices Using Multilayered Dielectrics for Nonvolatile Memory Applications 