A thickness-dependent interfacial distribution of oxide charges for thin metal oxide semiconductor (MOS) structures using high-k materials ZrO2 and HfO2 has been methodically investigated. The interface charge densities are analyzed using capacitance-voltage (C-V) method and also conductance (G-V) method. It indicates that, by reducing the effective oxide thickness (EOT), the interface charge densities () increases linearly. For the same EOT, has been found for the materials to be of the order of 1012 cm−2 eV−1 and it is originated to be in good agreement with published fabrication results at p-type doping level of  cm−3. Numerical calculations and solutions are performed by MATLAB and device simulation is done by ATLAS.

1. Introduction

A MOS device is generally fabricated by oxidizing a Si substrate and depositing a conducting film on the resulting amorphous SiO2 layer, forming the gate. The fabrication process always introduces defects at the SiO2-Si boundary that critically affects the device characteristics of both the diode and the transistor. Increasing the size of wafer and decreasing the size of device, that is device scaling, are sensible approaches to reduce the cost. According to International Technology Roadmap for Semiconductor (ITRS), the next generation Si-based MOS device will require oxide with thickness ~1 nm. With the ever-increasing requirement for speed and density of silicon integrated circuits (ICs), MOS device scaling has become a primary concern of the semiconductor manufacturing industry. But there are some essential scaling limits with the ultrathin oxide. The leakage current (tunneling current) increases exponentially with the reduction of gate insulator thickness that in turn results in intolerable power consumption and device performance problems. As a result, the scaling limit of SiO2 depends on both the elementary physics and accessible technology. It has been aimed towards achieving higher speed, lower power, lower cost, and higher density. Since the scaling of MOS devices utilizing SiO2 as gate material has reached its limit, there is a prospect in thinning the electrical oxide thickness by using high-k dielectric material and/or metal gates to achieve a greater physical thickness and thus reducing the direct tunneling current while retaining a low oxide thickness [14]. Several insulator materials of gate in the lanthanum group exhibiting higher dielectric constant as shown in Table 1, in the range of 7–30, have been proposed as prospective candidates for gate dielectric and show outstanding results.

There are many requirements that need to be satisfied before a new material is acceptable to the semiconductor industry for its use as gate dielectric. Though high-k dielectric materials look very promising, there are certain challenges and issues that have to be met before successful transition from SiO2 to high-k. The key guidelines for selecting an alternative dielectric are permittivity, band gap, band alignment to Si, thermal stability, film morphology, interface quality, compatibility with the current or expected materials to be used in processing for MOS devices, process compatibility, and reliability. In attempt to replace conventional SiO2 with new high-k materials, HfO2 and ZrO2 have received tremendous attention and are quite promising materials [58] considering their permittivity and conduction band offsets values.

High-k materials often suffer from poor electrical quality of the oxide dielectric-semiconductor interface and are often associated with lower dielectric breakdown voltages and decreased lifetimes. Moreover, with the introduction of high-k materials there occurs formation of interface charges. Due to the scaling, it has become very significant to consider the effect of generated traps in Si-SiO2 junction. The use of high-k gate dielectric generates a large number of interface traps at the surface channel and oxide trap charges in the gate dielectric bulk of MOS transistors, which would result in the degradation of device electrical characteristics. As the oxide thickness is reduced these interface trap charges become significant gradually. During the last three decades, gate oxide thickness was so large that this phenomenon was not noticeable, but nowadays it is a matter of importance to consider the interface states during MOS operation [912]. In this paper the interface charge densities have been measured and analyzed for thin MOS structure using ZrO2 and HfO2 high-k materials as gate dielectric.

2. Theoretical Analysis

Contributions are judged in terms of their extensive and debasing effect on the operational behavior of MOS devices; oxide-semiconductor interfacial traps must be considered as the most significant nonideality encountered in the MOS structure. Interface traps are allowed energy states in which electrons are localized in the vicinity of a material’s surface. All of the bulk centers are found to add levels to the energy band diagram within the forbidden band gap. SiO2 is often treated as an ideal insulator, where there are no traps or states at the interface of Si/SiO2. But in real devices, the Si/SiO2 interface and bulk SiO2 are far from being electrically neutral. These may be caused by positive or negative charges at the Si/SiO2 interface or by mobile ionic charges and fixed charges trapped within the oxide and itself, which are often created during the fabrication process. In reality, there are two types of charges that are associated with oxide layer, namely, interface trap charge and oxide charge. These charges play an important role affecting the physical and electrical properties of a MOS device. The features that distinguish interface trap charge from oxide charge are that interface charge varies with gate bias whereas oxide charge is independent of gate bias. The two thus have different effects on C-V characteristics. There are three types of oxide charges associated with the SiO2-Si system. They are fixed oxide charge, mobile oxide charge, and oxide trapped charge. All of these charges are very much dependent on the device fabrication process. Already in the pioneering work for understanding the physical properties of MOS structures, the capacitance-voltage (C-V) method was used to establish the main qualities of oxide-silicon interfaces.

Three insulator related parameters typically determined with C-V measurement are oxide charge density, , interface trap density, , and gate semiconductor work function difference, . They are determined from the flatband voltage: where is the permittivity of the oxide, is the permittivity of the free space, and is the oxide thickness. The fixed charge density and interface trap density (function of surface potential, ) are assumed to be located at the SiO2/Si interface and the remaining mobile ionic and oxide trap charge density, in the SiO2, leading to the flatband voltage expression for uniform oxide charge density,

On assuming that only is present in the oxide layer, then the equation becomes

But the most accurate and very sensitive method to extract the is the conductance method. Recently, the conductance method has been investigated and adapted for rigorously proving the electrical passivation of novel semiconductor-dielectric interfaces. The equivalent circuits [12] for conductance measurement in MOS capacitor are given in Figure 1. Figure 1(a) consists of the oxide (insulator) capacitance per unit area (), semiconductor capacitance per unit area (), interface trap capacitance per unit area () and interface trap resistance per unit area (). For the MOS interface charge analysis it is convenient to replace the circuit of Figure 1(a) with Figure 1(b): here is the equivalent parallel capacitance and the is the equivalent parallel conductance.

So the admittance of Figures 1(a) and 1(b) is given by where ( = measured frequency), , and is the magnitude of electronic charge.

If the real part and imaginary part are compared, respectively, we get

Dividing by makes it symmetrical in and is directly related to . It is more effective to calculate [12], because it has only a parameter related to interface trap without including . This equation considers the interface trap with single energy level in the band gap. For continuously distributed interface charge, we have to consider Figure 1(c), consisting of the measured equivalent parallel conductance () and measured capacitance (). Using this circuit, value (assuming negligible series resistance and tunnel conductance) is given,

can be calculated from the obtained versus graph from (5). At maximum , the is the inverse of ; approximate expression of can thus be given in terms of the measured maximum conductance as

3. Results and Discussion

Five groups of p-substrate MOS devices have been analyzed consisting of two high-k dielectric materials, ZrO2 and HfO2, having the dielectric constant of 22 for amorphous structure of the materials [13]. These materials were studied for different EOT at p-type doping level of 1 × 1017 cm−3. If a high-k material can replace SiO2, the dielectric thickness increases proportionally to keep the equal dielectric capacitance and EOT is the thickness of any dielectric material scaled by the ratio of its dielectric constant to the dielectric constant of SiO2 (). can be extracted from the slope of plot between flatband voltages and oxide thickness. By considering presence of only interface charge at the oxide-semiconductor interface the value of has been calculated theoretically and through simulation. Figure 2 shows the plot of magnitude of the flatband voltage as function of EOT for the high-k materials.

The graphs shown in Figure 2 clearly demonstrate the validity of our assumption in (3). The flat-band voltage of all the samples indicated negative value due to the existence of deep donor type surface states and positive interface charges. This noticeably indicates the presence of some parasitic charges at the interface. The deviation of simulated result from the theoretical result was found due to the high dielectric value of the materials. The theoretical interface charge present in each of the MOS capacitor was 5 × 1010 C at the interface. The simulated result obtained is shown in Table 2. Using the simulated C-V and G-V characteristics curve the values of the and have been measured, respectively, and the variation with frequency for the high-k dielectric materials has been shown in Figures 3 and 4.

The value of has been calculated using conductance method. It is a technique which replaces MOS capacitor with equivalent circuit model and calculates . Using the G-V curve conductance of the MOS has been calculated in depletion region of −1 V.

Figures 5(a) and 5(b) show the relationship of versus using ZrO2 and HfO2 high-k material of EOT at 1.77 nm, 2.65 nm, and 3.54 nm, respectively. This figure shows that the local maximum of each curve indicates the magnitude of . The peaks of the curves used for the oxide materials mean that the interface state energy levels are measured. Both and will peak as a function of bias voltage at gate terminal but only will peak as a function of frequency. will peak at a lower frequency when admittance is measured as a function of frequency with bias voltage at the gate as parameter or at the gate bias near to flatbands and when admittance is measured as a function of bias voltage at the gate with frequency as parameter. The characteristics of the graph are the same for these two materials and the is maximum at 1010 Hz. was calculated for the different EOT for ZrO2 and HfO2. The increase in is observed as the EOT is reduced as shown in Table 3 for a particular frequency of 1 MHz. This depicts that increases as the EOT reduces because density of trap charges is concentrated at the interface.

Figures 6(a) and 6(b) show the relationship between and for ZrO2 and HfO2 high-k material, respectively. The value of has been calculated at different frequencies using (5). At smaller frequencies the has a constant and high value. As the frequency reaches the inverse of interface trap time constant, the starts decreasing and at very high frequencies the value goes to a saturation region. The high value of at lower frequencies and a low value at higher frequencies are because trap charges are able to follow low frequencies and as the frequency increases trap charges cannot follow it so it does not contribute to at the large frequencies. The is predicted by conductance method for HfO2 with molecular beam deposition (MBD) process and for ZrO2 with atomic layer deposition (ALD) technique which is in resemblance to the fabrication results [14] at p-type doping level of 1 × 1017 cm−3.

4. Conclusions

The flatband voltage of all the samples indicated negative value due to the existence of deep donor type surface states and positive interface charges, and these effects are highly responsible for variation in with EOT. The interface charge densities have been calculated using C-V method as well as conductance method and it has been found that as the thickness of the oxide is reduced, the interface trap density increases for both HfO2 and ZrO2. This increase in by reducing the oxide thickness clearly demonstrates that the interface between oxide and silicon gets weaker.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.


The authors are highly indebted to the Department of Science and Technology (DST), Ministry of Science and Technology, Government of India, for supporting this technical work.