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Advances in Materials Science and Engineering
Volume 2016, Article ID 6303725, 9 pages
Research Article

Optimization of CNFET Parameters for High Performance Digital Circuits

Electronics, Communication, and Computer Engineering, Helwan University, Helwan, Egypt

Received 11 March 2016; Accepted 14 July 2016

Academic Editor: Anna Richelli

Copyright © 2016 Shimaa Ibrahim Sayed et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The Carbon Nanotube Field Effect Transistor (CNFET) is one of the most promising candidates to become successor of silicon CMOS in the near future because of its better electrostatics and higher mobility. The CNFET has many parameters such as operating voltage, number of tubes, pitch, nanotube diameter, dielectric constant, and contact materials which determine the digital circuit performance. This paper presents a study that investigates the effect of different CNFET parameters on performance and proposes a new CNFET design methodology to optimize performance characteristics such as current driving capability, delay, power consumption, and area for digital circuits. We investigate and conceptually explain the performance measures at 32 nm technologies for pure-CNFET, hybrid MOS-CNFET, and CMOS configurations. In our proposed design methodology, the power delay product (PDP) of the optimized CNFET is about 68%, 63%, and 79% less than that of the nonoptimized CNFET, hybrid MOS-CNFET, and CMOS circuits, respectively. Therefore, the proposed CNFET design is a strong candidate to implement high performance digital circuits.