Table of Contents Author Guidelines Submit a Manuscript
Advances in Materials Science and Engineering
Volume 2016, Article ID 6303725, 9 pages
http://dx.doi.org/10.1155/2016/6303725
Research Article

Optimization of CNFET Parameters for High Performance Digital Circuits

Electronics, Communication, and Computer Engineering, Helwan University, Helwan, Egypt

Received 11 March 2016; Accepted 14 July 2016

Academic Editor: Anna Richelli

Copyright © 2016 Shimaa Ibrahim Sayed et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. P. Wong, and F. Boeuf, “The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance,” IEEE Circuits and Devices Magazine, vol. 21, no. 1, pp. 16–26, 2005. View at Publisher · View at Google Scholar · View at Scopus
  2. J. M. Rabaey and S. Malik, “Challenges and solutions for late- and post-silicon design,” IEEE Design and Test of Computers, vol. 25, no. 4, pp. 296–302, 2008. View at Publisher · View at Google Scholar · View at Scopus
  3. Y. Sun and V. Kursun, “N-Type carbon-nanotube MOSFET device profile optimization for very large scale integration,” Transactions on Electrical and Electronic Materials, vol. 12, no. 2, pp. 43–50, 2011. View at Publisher · View at Google Scholar · View at Scopus
  4. S. Park, M. Vosguerichian, and Z. Bao, “A review of fabrication and applications of carbon nanotube film-based flexible electronics,” Nanoscale, vol. 5, no. 5, pp. 1727–1752, 2013. View at Publisher · View at Google Scholar · View at Scopus
  5. S. Lin, Y.-B. Kim, and F. Lombardi, “CNTFET-based design of ternary logic gates and arithmetic circuits,” IEEE Transactions on Nanotechnology, vol. 10, no. 2, pp. 217–225, 2011. View at Publisher · View at Google Scholar · View at Scopus
  6. F. Sharifi, A. Momei, and K. Navi, “CNFET based basic gates and a novel full adder cell,” International Journal of VLSI Design & Communication Systems, vol. 3, no. 3, 2012. View at Google Scholar
  7. I. S. Shimaa and H. G. Salah El-Din, “A novel high-speed adder-subtractor design based on CNFET,” International Journal of Applied Information Systems, vol. 10, no. 7, pp. 29–32, 2016. View at Publisher · View at Google Scholar
  8. P. Dhilleswararao, R. Mahapatra, and P. S. T. N. Srinivas, “High SNM 32nm CNFET based 6T SRAM Cell design considering transistor ratio,” in Proceedings of the 2014 International Conference on Electronics and Communication Systems (ICECS '14), pp. 1–6, Coimbatore, India, February 2014. View at Publisher · View at Google Scholar · View at Scopus
  9. S. I. Sayed, M. M. Abutaleb, and Z. B. Nossair, “Performance optimization of logic circuits based on hybrid CMOS and CNFET design,” International Journal of Recent Technology and Engineering, vol. 1, no. 6, pp. 1–4, 2013. View at Google Scholar
  10. D. Akinwande, S. Yasuda, B. Paul, S. Fujita, G. Close, and H.-S. P. Wong, “Monolithic integration of CMOS VLSI and carbon nanotubes for hybrid nanotechnology applications,” IEEE Transactions on Nanotechnology, vol. 7, no. 5, pp. 636–639, 2008. View at Publisher · View at Google Scholar · View at Scopus
  11. J. Deng and H.-S. P. Wong, “A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part I: model of the intrinsic channel region,” IEEE Transactions on Electron Devices, vol. 54, no. 12, pp. 3186–3194, 2007. View at Publisher · View at Google Scholar · View at Scopus
  12. J. Luo, L. Wei, C.-S. Lee et al., “Compact model for carbon nanotube field-effect transistors including nonidealities and calibrated with experimental data down to 9-nm gate length,” IEEE Transactions on Electron Devices, vol. 60, no. 6, pp. 1834–1843, 2013. View at Publisher · View at Google Scholar · View at Scopus
  13. P. Zhang, Y. Yang, T. Pei et al., “Transient response of carbon nanotube integrated circuits,” Nano Research, vol. 8, no. 3, pp. 1005–1016, 2015. View at Publisher · View at Google Scholar · View at Scopus
  14. F. A. Usmani and M. Hasan, “Carbon nanotube field effect transistors for high performance analog applications: an optimum design approach,” Microelectronics Journal, vol. 41, no. 7, pp. 395–402, 2010. View at Publisher · View at Google Scholar · View at Scopus
  15. L. Ding, S. Liang, T. Pei et al., “Carbon nanotube based ultra-low voltage integrated circuits: scaling down to 0.4 V,” Applied Physics Letters, vol. 100, no. 26, Article ID 263116, 2012. View at Publisher · View at Google Scholar · View at Scopus
  16. J. Deng, N. Patil, K. Ryu et al., “Carbon nanotube transistor circuits: circuit-level performance benchmarking and design options for living with imperfections,” in Proceedings of the 54th IEEE International Solid-State Circuits Conference (ISSCC '07), pp. 70–588, San Francisco, Calif, USA, February 2007. View at Publisher · View at Google Scholar · View at Scopus
  17. C. Kshirsagar, H. Li, T. E. Kopley, and K. Banerjee, “Accurate intrinsic gate capacitance model for carbon nanotube-array based FETs considering screening effect,” IEEE Electron Device Letters, vol. 29, no. 12, pp. 1408–1411, 2008. View at Publisher · View at Google Scholar · View at Scopus
  18. A. Raychowdhury, A. Keshavarzi, and J. Kurtin, “Optimal spacing of carbon nanotubes in a CNFET array for highest circuit performance,” in Proceedings of the 64th Device Research Conference, State College, Pa, USA, June 2006.
  19. A. Javey, H. Kim, M. Brink et al., “High-κ dielectrics for advanced carbon-nanotube transistors and logic gates,” Nature Materials, vol. 1, no. 4, pp. 241–246, 2002. View at Publisher · View at Google Scholar · View at Scopus
  20. R. Sahoo and R. R. Mishra, “Carbon nanotube field effect transistor: basic characterization and effect of high dielectric material,” International Journal of Recent Trends in Engineering, vol. 2, no. 7, pp. 40–42, 2009. View at Google Scholar
  21. Z. Chen, J. Appenzeller, J. Knoch, Y.-M. Lin, and P. Avouris, “The role of metal-nanotube contact in the performance of carbon nanotube field-effect transistors,” Nano Letters, vol. 5, no. 7, pp. 1497–1502, 2005. View at Publisher · View at Google Scholar · View at Scopus
  22. Y. Nosho, Y. Ohno, S. Kishimoto, and T. Mizutani, “Relation between conduction property and work function of contact metal in carbon nanotube field-effect transistors,” Nanotechnology, vol. 17, no. 14, pp. 3412–3415, 2006. View at Publisher · View at Google Scholar · View at Scopus
  23. Y. Chai, A. Hazeghi, K. Takei et al., “Low-resistance electrical contact to carbon nanotubes with graphitic interfacial layer,” IEEE Transactions on Electron Devices, vol. 59, no. 1, pp. 12–19, 2012. View at Publisher · View at Google Scholar · View at Scopus