Research Article  Open Access
Yuanying Qiu, Xun Qiu, Xianghu Guo, Dian Wang, Lijie Sun, "Thermal Analysis of Si/GaAs Bonding Wafers and Mitigation Strategies of the Bonding Stresses", Advances in Materials Science and Engineering, vol. 2017, Article ID 4903924, 8 pages, 2017. https://doi.org/10.1155/2017/4903924
Thermal Analysis of Si/GaAs Bonding Wafers and Mitigation Strategies of the Bonding Stresses
Abstract
In order to effectively reduce the thermal stresses of Si/GaAs bonding wafers during their annealing process, first of all, based on E. Suhir’s bimaterial thermal stress theory, the thermal stresses in the wafer bonding interfaces are analyzed and the thermal stress distribution formulas are obtained. Then, the thermal stress distribution curves of Si/GaAs bonding interfaces are investigated by finite element method (FEM) and are compared with the results from E. Suhir’s bimaterial thermal stress theory. Finally, some effective strategies are proposed to reduce the thermal stresses in the bonding interfaces.
1. Introduction
Wafer bonding is an important technology of the semiconductor process, in which wafers are directly attached under certain conditions. This technique can be mainly divided into three processes: surface treatment, prebonding, and annealing. During the annealing process, thermal stresses of prebonding wafers occur due to the different thermal expansion coefficients of the bonding materials. When the thermal stresses are too large, they will seriously affect bonding, resulting in a decrease in the quality and performance of the structure, even causing the wafers to be damaged. Thus, analyzing the mechanism and mitigation strategies of thermal stresses is of great importance to improve the quality of devices.
In this study, stresses in the wafer bonding interfaces are analyzed according to E. Suhir’s bimaterial thermal stress theory [1] and the analytical solution of thermal stress distribution in Si/GaAs wafer bonding interfaces is calculated. In ANSYS Workbench finite element analysis, the simulation solution of the thermal stresses is obtained and then compared with the results from the analytical solution.
There are various methods to analyze thermal stresses of bonding wafers. In [2–7], the thermal stresses of bonding materials were analyzed by using a twodimensional plane structure. But they did not analyze the annealing process from the threedimensional point of view and could not reflect the thermal deformation and thermal stress distribution. The references [2, 4, 6–9] analyzed the effect of annealing temperature on thermal stresses, while the influence of wafer thickness on thermal stresses was analyzed by [2, 5–7, 10]. The references [11, 12] analyzed the effect of annealing temperature on bonding strength. The influence of wafer thickness on bonding strength was analyzed by [13]. But only one or two measures were proposed to reduce the thermal stresses considering the annealing temperature or wafer thickness; the analysis of the factors which affect the thermal stresses was not comprehensive yet.
Planar and crosssectional distributions of thermal stresses in the bonded InP/Si pairs were analyzed by the twodimensional finite element method in [14]; the authors analyzed the effect of annealing temperatures and wafer thicknesses on the thermal stresses by an analytic method. But [14] did not combine theory and finite element analysis to discuss the measures to reduce the thermal stresses, and the distributions of thermal stress were not concrete. In view of the research results and limitations mentioned above, this paper aims at the bonding problems of Si and GaAs. The thermal stresses of the bonding wafers are analyzed through both E. Suhir’s bimaterial thermal stress theory and threedimensional finite element simulation. The visual displacement contours and the stress curve diagrams are obtained and the approaches to mitigate the adverse effect of thermal stresses are proposed and studied.
Besides the thermalmismatch stresses, the latticemismatch stresses are the other type of stresses in the bimaterial semiconductor. E. Suhir compared these two types of stresses by the theoretical derivation and several examples in [15]. As for the latticemismatch stresses, an effective and physically meaningful analytical predictive model was developed to evaluate the latticemismatch stresses in a semiconductor film grown on a circular substrate by E. Suhir in [16], and it was concluded that the shearing stress of the theoryofelasticity prediction was larger than that of the strengthofmaterial one.
As mentioned above, the thermalmismatch stresses and the latticemismatch stresses are two types of stresses. This paper focuses on the thermalmismatch stresses of the Si/GaAs bonding wafer by Suhir’s bimaterial thermal stress theory [1] and threedimensional finite element simulation. As for the latticemismatch stresses of the Si/GaAs bonding wafer and the comparison between its latticemismatch stresses and the thermalmismatch stresses, they will be discussed in the near future.
2. Model and Analytical Equation of the Thermal Stresses
In this study, we mainly discuss the bonding condition of Si and GaAs. Set the thickness of Si to 50 , Young’s modulus to , Poisson’s ratio to , and the coefficient of thermal expansion to . Set the thickness of GaAs to 300 , Young’s modulus to , Poisson’s ratio to , and the coefficient of thermal expansion to . Both of the radii of two wafers are 5 mm. Both the upper and the side surfaces of Si and the side surface of GaAs are all unconstrained, while the lower surface of Si and the upper surface of GaAs are bound constraints. And the wafers are placed on a rigidity plane. The temperature changes from 300°C to 20°C. The temperature change is set to be uniform, the bonded wafer interface is without cavity, the thermal expansion coefficient is linear, elastic, and isotropic, and material parameters are independent of time and temperature [2]. Meanwhile, assume that the wafers are free of stress at their initial annealing temperature (300°C).
When the temperature changes, the shearing stresses , peeling stresses , and normal stresses (radial normal stresses and circumferential normal stresses ) are generated near the surface of the bonding wafers. The shearing stresses and normal stresses are parallel to the bonding interfaces, and the peeling stresses are perpendicular to the bonding interfaces. Figure 1 shows the stresses distribution during the annealing process, and the circumferential normal stress is perpendicular to the plane.
Figure 1 is the schematic diagram of the bonding structure of two circular wafers with the same diameter and the total thickness is (the thickness of Si is and the thickness of GaAs is ). is the shearing force (the direction of the force is parallel to the bonding interfaces) per unit width (axis) of the wafer bonding interfaces. The thickness of the bonding wafers is small, so the shearing force can be regarded as a uniform distribution in the direction of wafer thickness, so
In this equation, is the shearing stress per unit length (axis) of bonding interfaces and is the radius of the wafers.
To investigate the force and equilibrium of the bonding wafers at the cross section, the moment balance equations of thecross section arewhereandare two bending moments at thecross section of the wafers:where the effective Young moduli of the two wafers are and , andare Young’s moduli of the two wafers, andare Poisson’s ratios of the two kinds of materials, and is the radius of curvature of the bonding wafers.
According to Suhir’s bimaterial thermal stress theory, the shearing stresses in the bonding interfaces are [17]where , , where is the lateral (axis) flexibility coefficient of the wafers, , where and are the coefficients of bending stiffness of two wafers, , where and are the longitudinal (axis) flexibility coefficients of two wafer bonding interfaces, , where and are the thermal expansion coefficients of the two kinds of materials, and is the high and low temperature difference during the annealing process.
The peeling stresses are [17]where , , , and .
The radial normal stresses (tensile stress or compressive stress) are determined by the shearing forceand bending momentof the wafers. Combining formulas (1), (3), and (4), we can get the expression of the radial normal stresses of Si and GaAs bonding interfaces [18]:where “+” indicates that the radial normal stress is tensile stress and “−” indicates that the radial normal stress is compressive stress. This is because the thermal expansion coefficient of GaAs is larger than that of Si. In the cooling process, the shrinkage of GaAs is larger than the shrinkage of Si, leading to GaAs being subjected to tensile stress and Si being subjected to compressive stress.
3. Finite Element Thermal Analysis of the Structure
In this study, the finite element method is utilized to analyze the bonding stresses between Si and GaAs and the stress curves are obtained. The result is compared with that from Suhir’s bimaterial thermal stress theory in the twodimensional space. Further, the finite element method is extended to threedimensional space, and the visual displacement contours of the structure are given.
The circular structure model is established by SolidWorks, as shown in Figure 2, and the local finite element model is shown in Figure 3. The plane of the circular disk structure is a horizontal plane ( plane), and theaxis is perpendicular to the disk structure. Hexahedral meshes are used in the overall structure, and the mesh density on the edge of the structure is increased by the manual intervention in order to get a more accurate result.
We can obtain the curves of the shearing stress, peeling stress, and radial normal stresses in the bonding interfaces at 20°C by theoretical expression of the thermal stresses and FEM software ANSYS Workbench, respectively, as shown in Figures 4, 5, and 6.
(a) Radial normal stress of Si
(b) Radial normal stress of GaAs
Figures 4, 5, and 6 show that the shearing stress, peeling stress, and radial normal stresses of the bonding interfaces change obviously in the edge area of the wafers (radius 4.5 mm–5 mm). It can be seen from the figures that the distributions and variation trends of the thermal stresses from the theoretical solution are similar to those from the simulation solution. In addition, the theoretical solution curves of shearing stress and finite element simulation solution of shearing stress are basically coincident, and mutual verifications are obtained. But the relative error of the maximum radial normal stress of Si is ()/110 = 20.5%, while the relative error of the maximum radial normal stress of GaAs is ()/75.1 = 26.9%. The reasons of that are some approximate calculations in the theoretical solution and the certain errors in the simulation solution. By the finite element simulation analysis, the shearing stresses and peeling stresses of the two kinds of materials are exactly the same; this is consistent with the results of formulas (4) and (5) in the second section. Therefore, only one shearing stress and one peeling stress are analyzed. The radial normal stresses and circumferential normal stresses are the same, which are perpendicular to each other and parallel to the bonding interfaces, so it is only necessary to analyze the radial normal stresses.
4. Thermal Deformation Analysis of the Structure
As shown in Figure 7, when the temperature of the structure is changed from 300°C to 20°C, the displacement contours in the axis and axis are generated
(a) The displacement contour in direction
(b) The displacement contour in direction
During the annealing process, as the temperature decreases from 300°C to 20°C, the bonding wafers indirection and direction shrink due to cold contraction, resulting in negative displacement in direction. As shown in Figure 7(a), the displacement direction is on the positive half axis of, and the displacement is negative. The displacement direction is +on the negative half axis of, and the displacement is positive. The maximum displacement values of direction and direction are both 0.010519 mm, and their ratio to the radius is 0.010519/5 = 0.0021. In the bonding structure, Si is the upper layer and the lower layer is GaAs. The linear expansion coefficient of GaAs is , which is larger than that of Si, resulting in the shrinkage of GaAs being bigger than that of Si during the cooling process and the bonding structure protruding upwards. The maximum displacement in direction is 0.037991 mm and its ratio to the wafer thickness is 0.037991/0.35 = 0.1085457. It can be seen that the relative displacement of the wafers in the axial direction is larger than that in the radial direction, but both of them are small.
As shown in Figure 7(a), the radial and circumferential displacement values at the edge of the wafers are larger, and the wafer interface is easier to slip and promotes the diffusion of dislocations. Thus, the shearing stresses and peeling stresses in the bonding interfaces are almost zero in the center of the wafers and increase dramatically in the edge area. From Figure 7(b), due to the effect of the bending moment, the central region of the structure protrudes upwards. From formulas (1) and (2) in Section 2, it can be seen that the bending moment from the center to the edge is reduced to 0. The normal stresses are mainly affected by the bending moment and the shearing force, which confirms the trend from the center to the edge.
5. Mitigation Strategies of Thermal Stresses in the Bonding Interfaces
5.1. Analysis of Different Radius Bonding Structures
From the above analysis, it can be clearly seen that the normal stresses (the radial normal stresses and circumferential normal stresses) are the main factors of the failure of the central region in the wafers and the shearing stresses and peeling stresses are the main reasons for the failure of the edge in the wafers. According to these features, the radial normal stresses away from the edge region of the wafers are studied with different radii. The radii are arranged as 5 mm, 10 mm, 20 mm, 30 mm, 40 mm, and 50 mm, respectively, as shown in Table 1.

Based on the finite element simulation analysis, it can be found that the radial normal stresses away from the edge of different radius structures are basically unchanged, while the shearing stresses and peeling stresses are basically zero in the central area. Therefore, in the actual production process within a certain radius, in order to effectively reduce the thermal stresses of the structure, the radii of wafers can be increased, that is, larger than the 10% required, and then the thermal stresses can be reduced by means of cutting the edge of the wafers.
5.2. Effect of the Annealing Temperature
According to the theoretical analysis of the second section, the annealing temperature affects the thermal stresses of the bonding interfaces. From the above modeling results, it is noted that the peeling stresses and shearing stresses at the edge area are the largest ones, while the normal stresses at the edge area are the minimum. The peeling stresses and shearing stresses away from the edge area are zero, while the normal stresses get their maximum at the edge area. Figure 8 shows the curves of maximum thermal stresses in the bonding interfaces at room temperature with different annealing temperatures (data from Si/GaAs bonding wafers with a radius of 10 mm).
As shown in Figure 8, it is noted that the magnitude of thermal stresses increases linearly with the increase of annealing temperature. The higher the annealing temperature is, the greater the thermal stresses are. Therefore, reducing the annealing temperature is one of the effective methods to reduce the thermal stresses under the condition that the wafers can be properly bonded.
5.3. Effect of the Thicknesses of Si and GaAs
Figure 9 shows the curves of maximum value of thermal stresses (shearing stresses, peeling stresses, and radial normal stresses) in the Si/GaAs bonding interfaces with a radius of 10 mm at 20°C with the various wafer thicknesses when the annealing temperature is 300°C.
(a) Maximum thermal stresses with different thicknesses of Si
(b) Maximum thermal stresses with different thicknesses of GaAs
Figure 9(a) indicates that when the thickness of GaAs is 0.3 mm, the maximum values of thermal stresses change with the increase of the thickness of Si. Figure 9(b) shows that the maximum values of thermal stresses vary with the change of the thicknesses of GaAs when the thickness of Si is 0.05 mm.
It can be seen from Figure 9 that when the thickness of GaAs is 0.3 mm, the thermal stresses increase gradually as the thickness of Si increases from 0.01 to 0.05 mm. The shearing stress and peeling stress are almost unchanged in the range of 0.05 to 0.4 mm. The radial normal stresses decrease slowly as the thickness of Si increases from 0.1 to 0.4 mm.
As the thickness of Si is 0.05 mm, the thermal stresses have local minimum as the thickness of GaAs is 0.05 mm. The shearing stress and peeling stress are almost constant in the 0.1–0.4 mm range. The radial normal stress decreases when the thickness of Si increases from 0.15 to 0.4 mm.
From Figure 9(a), it can be seen that when the thickness of GaAs is 0.3 mm and the thickness of Si is 0.05 mm, the radial normal stress is relatively small and the peeling stress and shearing stress increase slightly. From Figure 9(b), it is noted that when the thickness of Si is 0.05 mm and the thickness of GaAs is 0.1 mm, the radial normal stress is relatively small, and the peeling stress and shearing stress increase slightly. These two structures can effectively alleviate the adverse effect of thermal stresses in the bonding interfaces.
6. Conclusion
In this study, the thermal stresses in the bonding interfaces are analyzed by Suhir’s bimaterial theory. The thermal stress distribution in the bonding interfaces is obtained and the results are compared with the FEM simulation solutions. Based on the comparison, the following conclusions can be made:(1)By analyzing the thermal stresses (the shearing stresses, peeling stresses, and normal stresses) in the bonding interfaces, the theoretical analysis is consistent with the FEM simulation results. The shearing stresses and peeling stresses are zero in most areas of the center, but they only increase abruptly in the edge region. The radial normal stresses are certain values in most areas of the center, and they gradually reduce to zero in the edge region. In view of the analysis above, in a certain radius, in order to effectively reduce the thermal stresses, we can make wafer radius 10% larger than that required, and then the thermal stresses can be reduced by means of cutting the edge of the wafers.(2)Under the condition that the wafers can properly be bonded, decreasing the annealing temperature is an effective approach to reduce the thermal stresses.(3)As the thickness of Si is 0.05 mm and the corresponding thickness of GaAs is 0.1 mm or the thickness of GaAs is 0.3 mm and the corresponding thickness of Si is 0.05 mm, the radial normal stresses are relatively small, and the peeling stresses and shearing stresses increase slightly, which can greatly reduce the thermal stresses in the bonding interfaces. Therefore, the adverse effect of thermal stresses on bonding can be mitigated by changing the thickness of the two bonding wafers.
7. Future Work
The anticipated future work should include but might not be limited to the following major efforts:(1)This paper aims at a bonding wafer with a thin Si on top of a thick GaAs for a solar cell specially. A reversed scenario with a thin GaAs on top of a thick Si in the common practical applications will be researched in the next research paper.(2)This paper focuses on the thermalmismatch stresses in the bonding wafer for a solar cell. However, it is a meaningful subject to explore the latticemismatch stresses and the comparison between the latticemismatch stresses and the thermalmismatch stresses in bonding wafers in the next research paper.
Conflicts of Interest
The authors declare that they have no conflicts of interest.
Acknowledgments
This work was financially supported by the Shanghai RisingStar Program (no. 14QB1402800).
References
 E. Suhir, “Stresses in Bimetal thermostats,” Journal of Applied Mechanics, Transactions ASME, vol. 53, no. 3, pp. 657–660, 1986. View at: Publisher Site  Google Scholar
 L. Yu and L. Yan, “Analysis of the stress of GaAs/InP bonded interface,” Research and Progress of Solid State Electronics, vol. 32, no. 2, pp. 120–125, 2012 (Chinese). View at: Google Scholar
 G. He, G. Yang, W. Zheng et al., “Analysis of Si/GaAs bonding stresses with the finite element method,” Chinese Journal of Semiconductors, vol. 27, no. 11, pp. 1906–1910, 2006. View at: Google Scholar
 Z.Q. Liu, L.C. Wang, L.J. Yu et al., “Theoretical analysis on thermal stress in interface of InP/Si bonded wafers,” Semiconductor Optoelectronics, vol. 27, no. 4, pp. 429–433, 2006 (Chinese). View at: Google Scholar
 S. Ogawa, M. Imada, and S. Noda, “Analysis of thermal stress in wafer bonding of dissimilar materials for the introduction of an InPbased light emitter into a GaAsbased threedimensional photonic crystal,” Applied Physics Letters, vol. 82, no. 20, pp. 3406–3408, 2003. View at: Publisher Site  Google Scholar
 B.W. Lin, N.J. Wu, Y. C. S. Wu, and S. C. Hsu, “A stress analysis of transferred thinGaN lightemitting diodes fabricated by AuSi wafer bonding,” IEEE/OSA Journal of Display Technology, vol. 9, no. 5, pp. 371–376, 2013. View at: Publisher Site  Google Scholar
 H.Q. Zhao, L.J. Yu, Y.Z. Huang, and Y.T. Wang, “Strain analysis of InP/InGaAsP wafer bonded on Si by Xray double crystalline diffraction,” Materials Science and Engineering B: SolidState Materials for Advanced Technology, vol. 133, no. 1–3, pp. 117–123, 2006. View at: Publisher Site  Google Scholar
 X. Zheng, W. Chen, and X. Chen, “Stress in Siglass anodic bonding and its effect on silicon piezoresistive pressure sensor,” in Proceedings of the 5th IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS '10), pp. 524–527, January 2010. View at: Publisher Site  Google Scholar
 T. Izuhara, M. Levy, and R. M. Osgood Jr., “Direct wafer bonding and transfer of 10μmthick magnetic garnet films onto semiconductor surfaces,” Applied Physics Letters, vol. 76, no. 10, pp. 1261–1263, 2000. View at: Publisher Site  Google Scholar
 J. M. Hartmann, F. Andrieu, D. Lafond et al., “Reduced pressurechemical vapour deposition of Si/SiGe heterostructures for nanoelectronics,” Materials Science and Engineering: B, vol. 154155, no. 1–3, pp. 76–84, 2008. View at: Publisher Site  Google Scholar
 N. Malik, K. SchjølbergHenriksen, E. Poppe, M. M. V. Taklo, and T. G. Finstad, “AlAl thermo compression bonding for waferlevel MEMS sealing,” Sensors and Actuators, A: Physical, vol. 211, pp. 115–120, 2014. View at: Publisher Site  Google Scholar
 T. Plach, K. Hingerl, S. Tollabimazraehno, G. Hesser, V. Dragoi, and M. Wimplinger, “Mechanisms for room temperature direct wafer bonding,” Journal of Applied Physics, vol. 113, no. 9, Article ID 094905, 2013. View at: Publisher Site  Google Scholar
 X. Wang, Y. Yu, and J. Ning, “Researching the silicon direct wafer bonding with interfacial SiO_{2} layer,” Journal of Semiconductors, vol. 37, no. 5, Article ID 056001, 2016. View at: Publisher Site  Google Scholar
 H.Q. Zhao, L.J. Yu, and Y.Z. Huang, “Thermal stress analysis for GaInAsP multiple quantum well wafer chemically bonded to Si (100),” Journal of Applied Physics, vol. 100, no. 2, Article ID 023513, 2006. View at: Publisher Site  Google Scholar
 E. Suhir, “Stresses in bimaterial GaN assemblies,” Journal of Applied Physics, vol. 110, no. 7, Article ID 074506, 2011. View at: Publisher Site  Google Scholar
 E. Suhir, S. Yi, J. Nicolics, G. Khatibi, and M. Lederer, “Semiconductor film grown on a circular substrate: predictive modeling of latticemisfit stresses,” Journal of Materials Science: Materials in Electronics, vol. 27, no. 9, pp. 9356–9362, 2016. View at: Publisher Site  Google Scholar
 B. Chen, X.Y. Wang, H. Huang, Y.Q. Huang, and X.M. Ren, “Thermal stress in IIIV group semiconductor wafer bonding,” Bandaoti Guangdian/Semiconductor Optoelectronics, vol. 26, no. 5, pp. 421–427, 2005 (Chinese). View at: Google Scholar
 Z. Zhou, X. Kong, Y. Huang, and X. Ren, “Theoretical analysis of stresses in interface of bonded wafers,” Chinese Journal of Semiconductors, vol. 24, no. 11, pp. 1176–1179, 2003 (Chinese). View at: Google Scholar
Copyright
Copyright © 2017 Yuanying Qiu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.