Design and Optimization of Polarization Splitting and Rotating Devices in Silicon-on-Insulator Technology

Table 1

Comparison among different PMC architectures.

Device	Performance	𝐵𝑊	𝐿	Etch step
[26]	PER = 15 dB	300 nm	40 μm	2
Device #1	PER = 26 dB; PCE = 99.7%	100 nm	25 μm
[30]	PER = 16 dB; PCE = 97.5%	47 nm	10 μm	1
Device #2	PER > 17 dB; PCE > 98%	50 nm	5 μm
[31]	PCE = 82.2%	30 nm	25 μm	2
Device #3	PER > 17.5 dB; PCE = 98.3%	20 nm	29 μm
[32]	PCE ≃100%	70 nm	100 μm	1
Device #4	PER = 39 dB; PCE ≃100%	170 nm	75 μm