Research Article

One Clock-Cycle Response 0.5  𝜇 m CMOS Dual-Mode Σ Δ DC-DC Bypass Boost Converter Stable over Wide 𝑅 E S R L C Variations

Figure 6

Simplified conceptual circuit schematic of the dual-mode Σ Δ converter in bypass mode, as the bypass loop virtually shorts 𝑣 𝑆 and 𝑉 R E F and the current loop regulates 𝑖 𝐿 to 𝑣 I . R E F / 𝑅 𝐼 .
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