Advances in Power Electronics

Volume 2013, Article ID 381581, 13 pages

http://dx.doi.org/10.1155/2013/381581

## Selection of Design Parameters to Reduce the Zero-Sequence Circulating Current Flow in Parallel Operation of DC Linked Multiple Shunt APF Units

School of Electrical & Electronic Engineering, Dublin Institute of Technology, Kevin Street, Dublin 08, Dublin, Ireland

Received 30 April 2013; Revised 11 October 2013; Accepted 28 October 2013

Academic Editor: Gabriele Grandi

Copyright © 2013 Shafiuzzaman K. Khadem et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

Capacity enhancement and operational flexibility are two of the important limitations of the centralized shunt APF () unit. These limitations can be conquered by the operation of multiple APF units in parallel and connected back to back by a common DC link capacitor. In that case, a circulating current (CC) flows within the units. This CC flow becomes out of control when the units operate in hysteresis based current controlled mode. One of the difficulties of this CC flow control or reduction is the variable switching frequency of the units. In this paper, the model for CC flow is derived by the switching dynamics study of the units. It is found that the selection of design parameters plays an important role in the amount of CC flow. Detailed simulation, analysis, and real-time performance show how the selection of design parameters affects the CC flow and the reduction of CC flow can also be achieved at an acceptable level by the proper selection of design parameters.

#### 1. Introduction

The power quality, at all time, is a matter of concern where a number of nonlinear, harmonics producing, and sophisticated loads are connected in an electrical distribution network. In that case, for power quality (PQ) improvement, shunt active power filters () are finding greater applications as interfacing and compensating devices in the distributed network. The power rating and switching frequency of the converters are determined by the magnitude of harmonic currents and required filter bandwidth. In high power applications, the filtering task cannot be performed for the whole spectrum of harmonics by using a single converter due to the limitations on switching frequency and power rating of the semiconductor devices. Therefore, compensating the reactive harmonic components to improve the power quality of the distributed network as well as to avoid the large capacity centralised , parallel operation of multiple low power units is increasing. Different controlling mechanisms and topologies are available in handling the difficulties of parallel operation of either in active load sharing or distributed mode. Although the harmonic current compensation is the primary function of parallel APF, it can also be used as a compensator for voltage harmonics. A detailed technical review on parallel operation of for current and voltage harmonic compensation in a distributed generation (DG) network has been done in [1, 2] where the pros and cons of the different control methods have been discussed. For these cases, there is no physical/electrical link between the units. Another kind of configuration is also available where the system components and cost are reduced by maintaining a common DC link back-to-back connection between the units [3]. But it then raises the control complexity by introducing the zero-sequence circulating current (ZSCC) flow within the units which can overload the inverters of the APF units and thus increases the power losses. Other problems associated with the ZSCC flow is that it can reduce the ampacity (capacity of carrying current) of the cable, it can increase the DC link voltage, and it is harmful for the DG system like DFIG application [4–8].

The control methods for the reduction of ZSCC discussed in the literature are mainly for PWM based control system. In most of the cases, the methods are discussed for the parallel operation of inverter or rectifier [6–10]. Very few of the articles show the ZSCC reduction for the parallel operation of units [11]. None of these discuss the ZSCC flow issues and control method for the parallel operation of converter/ based on hysteresis control. Therefore, an attempt has been made here to discuss the issues related to hysteresis control.

#### 2. Working Principle

According to the working principle of an unit in parallel to the load to compensate the reactive and harmonic current, there are two possible modes of operation: capacitive mode (where the current flows from the capacitor) and inductive mode (the current flows towards the capacitor). When multiple APF units work in a current sharing mode, there could be four possible modes of operation: (i) capacitive-capacitive, (ii) inductive-inductive, (iii) capacitive-inductive, and (iv) inductive-capacitive. As an example, Figure 1(a) shows a single line diagram of a 3-phase system, where represents the circulating current flow between the APF units. In the case of a 3-phase system, shown in Figure 1(b), this circulating current flow exists as a zero-sequence harmonics in the zero-sequence current flow when a circulating loop is created within the units and hence it is termed zero-sequence circulating current (ZSCC) flow. In general these harmonics are () order, where .

#### 3. Model for ZSCC Flow

For simplicity, derivation of ZSCC flow has been carried out on a per phase basis. Figure 2 shows the possible mode of operation between the APF units (1 phase), where sh- and sh- represent the corresponding inductive and capacitive mode, respectively. If there is a difference in any of the parameters, such as switching frequency, current sharing, interfacing inductor, and hysteresis band (in case of hysteresis current controller), then the units can operate in inductive-capacitive or capacitive-inductive mode. In these cases, ZSCC will flow and these are reflected in Figures 2(f) and 2(h).

From Figures 2(a) and 2(b), during the capacitive mode, the current flow can be obtained as while ; here is the ducy cycle; that is, the Ac voltages of the units are equal.

Similarly, Figures 2(c) and 2(d) show that when both the APF units work in inductive mode during its switching cycle, the resulting current flows can be found as while .

From Figures 2(e) and 2(f), the circulating current flow in capacitive-inductive mode can be obtained as while .

Similarly, the circulating current flow for inductive-capacitive mode is while .

Therefore, in general, the equation for the ZSCC flow can be written as where for capacitive mode and for inductive mode.

The possible maximum value for CC flow () in one leg can be obtained as where , , and are the switch and switching time, as shown in Figure 1, respectively. The possible value of can be obtained as . Here, and is the time period.

For 3-phase system, the ZSCC can be found as where and are the zero-sequence components of the units.

This is also confirmed in [11] for topology analysis based on a parallel interleaved inverter. It is also similar to the rectifier analysis in [6]. In most of the research articles, derivation or ZSCC cancellation has been carried out for two inverters or units [7–11]. Moreover, the control methods discussed in the literature are mainly for PWM based control system. None of them discuss the CC flow issues for the parallel operation of APFs based on hysteresis control. Therefore, an attempt has been made here to discuss the issues related to hysteresis control.

#### 4. Control Issues for the ZSCC Flow

There are mainly two ways to eliminate or reduce the ZSCC flow: (i) breaking the route of CC flow by introducing physical devices such as an isolation transformer or common mode inductor or (ii) by proper control methods. From the derivation of ZSCC flow it is found that the CC value depends on the duty cycle () or switching frequency (), DC link voltage (), and the interfacing inductor () of the APF units. Therefore, before selecting the control method for multiple units with a common Dc link, some design consideration should be made to reduce the CC flow. The design options that can be implemented to reduce the CC flow are as follows.(i)Decrease the . According to the design criteria of single/3-phase APF_{sh} system there is a minimum value of that has to be maintained to compensate the reactive and harmonic current.(ii)As the , reducing the and decreasing the difference between the or will reduce CC flow.(iii)Reduced will further increase the (in the case of hysteresis current control) and it will then in turn reduce the circulating current flow. But increased will reduce the VAR rating of APF_{sh}.

It is also clear from the derivation that the CC flow does not directly depend on the compensating current rating of the units. Therefore, once the current or VAR rating of is fixed, the design components ( and ) should be chosen in such a way so that the is possibly high and the difference between the units is as low as possible. In that case, introducing the common mode inductor in the units can be a better choice. Implementation of a CC control method in the control strategy will further reduce the CC flow. But it will then increase the control complexity.

#### 5. Selection of Control Method for Units

With the control issues of the CC flow in mind, selection of a control strategy for the units should be made. Different control strategies for parallel operation of multiple APF units were reviewed [1, 2]. In general, control can be based on active current sharing where the compensating power/current can be divided equally or up to the compensating capacity of the APF units. Another prominent control is droop control where information exchange between the APF units is required. For simplicity, a current sharing (power splitting) method based on hysteresis current control has been chosen for the remainder of the analysis. The control of switches mainly depends on the control method for the APF units. In the case of the current sharing method, the switching can be determined by current sharing (equally distributed) or a capacity limitation technique. As an example, if , , , and are the Rms values of APF compensating current, reference compensating current, rated current, and the switching reference current for ON/OFF condition, then for the current sharing technique where and for the capacity limitation technique.

#### 6. Simulation Study

In-depth information on parallel operation of multiple based on hysteresis current controller is not available yet, especially in the case of ZSCC flow. Therefore, in the present work, the objective is to reduce the ZSCC flow based on the design parameter selection. Two units of have been modelled here to operate in power sharing mode. In terms of sharing the following proportions have been chosen:(A) and ; each APF_{sh} compensates half of the load reactive and harmonic components,(B); and ,(C); ; and ,(D); ; and .

In the case of a hysteresis current control based , according to the selection of design parameters for , described in [12–14] and the control issues of CC flow, the CC flow can be reduced by the proper selection of the design components including , , , and . As the is fixed, variation of other components has been made here to analyze the reduction of CC flow. Results and discussion are given below.

Table 1 shows the parameters that have been considered for the proportion (A), as mentioned above. Corresponding results have been given in Figure 3 and discussed below.

Figure 3 shows the performance study of the two units in power sharing mode for the cases A1a–A5a where each of the units compensates half of the load reactive and harmonic components. starts working at the beginning, whereas starts at 0.5 sec. As there is no ZSCC that occurs before 0.5 sec, therefore the ZSCC waveforms for the corresponding simulations have been shown in A1b–A5b from 0.55 sec to 0.75 sec. For the cases A1–A3, the switching frequency of both units was equal and the variations have been made for and . Cases A1 and A2 show that the possible CC flow can be zero when and ; that is, both the units are identical. Although the rating and of each unit are the same, ZSCC can flow as shown in case A3. This happens due to the difference in design parameters and . Cases A4, and A5 show the results for different , , and . For both the cases, ZSCC flows. In a comparison with A3, A4 and A5, A5 shows better results in the reduction of ZSCC flow. It is due to the higher values of and lower values of , though the parameter is different.

Table 2 shows the parameters that have been considered for the proportion (B). Corresponding results have been given in Figure 4 and discussed below.

Figure 4 shows that, for all the cases, ZSCC flows. Even though the values are different, the reduced ZSCC flow occurs in the case of B5 where the values for are high and are low compared to other cases. The worst case occurs for B2 where is low and is high.

Tables 3 and 4 show the parameters for the cases C and D where the sharing proportion is different than that for A and B. For both the cases, values of are kept low, whereas the values for are high. In both cases, are equal. And the same components have been chosen for D where the compensating current is two times higher than that of case C.

Figure 5 shows the performances for the cases C and D in terms of ZSCC flow. In both cases, ZSCC flow is the same even though for case D, units are compensating higher current than that of C. These results indicate that the ZSCC flow does not depend on the amount of compensating current. These ZSCC flows are higher than that of A and B and this is due to the lower values of .

Finally, a comparison has been made for the ZSCC between the A3–A5 and A6–A8 cases for one cycle, as shown in Figure 6. For A3, is the same for both of the units, whereas for A4 and A5 it is different. But the values of are comparatively higher for A5. Therefore, within A3 to A5, the ZSCC flow is comparatively lower in the case of A5, as shown in Figure 6(a).

For the cases A6–A8, the switching frequency () of is reduced and therefore the value of increases, as shown in Table 1. At the same time, the switching frequency difference between the units is also reduced. The performance of the units in terms of ZSCC flow for these cases is reflected in Figure 6(b). This shows that ZSCC flow can further be reduced by reducing the (to increase the value of ) and the difference between the of the units. The reduction of zero-sequence harmonics content for the cases A6–A8 is also shown in Figure 7, where it shows that the magnitude of zero-sequence harmonics components in the compensating current is reduced gradually for the cases from A6 to A8. This also confirms the outcome as shown in Figure 6.

But it also has to be kept in mind that increasing could increase the THD at the PCC, as given in Table 1. Therefore, in terms of design criteria for the selection of units to place in multiple units with common DC link system, one should consider the higher values of and lower the difference between of the units with care about THD.

#### 7. Real-Time Performance Study

With the advancement of technology, real-time performance of any system can be observed using a real-time simulator. Instead of developing the complete actual system at full capacity, the controller/system can either be modelled in software or can be built in hardware or can be a combination of both. In real-time simulation, the accuracy of the computations depends upon the precise dynamic representation of the system and the processing time to produce the results [15].

An electrical power system including 2 units of has been modelled in MATLAB using RT-LAB (real-time simulation) tools to observe the performance in the real-time environment. The system is then tested in SIL (Software-in-Loop; both the controller and the plant are simulated in real-time in the same simulator) with the hardware synchronization mode (data communication is in real-time through the ADC/DAC) which is similar to hardware-in-loop (HIL) test. Figure 8 shows the real-time simulation structure in a SIL configuration used to develop the real-time environment by OPAL-RT. With the combination of MATLAB SPS (Sim Power System) from MATHWORKS and the RT-LAB toolbox from OPAL-RT, the real-time model of the power system and controller is developed for the real-time simulator.

Figure 9 shows the results for the cases A6, A7, and A8, where both the units are compensating harmonic current in a power sharing mode. The waveform of the utility current () contains fewer harmonics for A7 compared to A6 and A8. This happens because of the moderate value of and for A7 compared to that of A6 ( is too low) and A8 ( is too high). Therefore, the THD value is also reduced.

For the case of A8, although the THD increases, ZSCC is reduced. Figures 10(a), 10(c), and 10(e) show the ZSCC flow for these (A6–A8) cases and it clearly depicts the gradual reduction of ZSCC from A6 to A8. It is also clear from the zoom-in for one cycle study in Figures 10(b), 10(d), and 10(f) that a considerable amount of ZSCC can be reduced by proper selection of design parameters for the units to operate in load sharing mode. Thus, it validates the simulation, analysis of the performance, and ZSCC flow study.

#### 8. Conclusion

Capacity enhancement and operation flexibility are two of the important limitations of the centralized unit when placed in a DG integrated network, especially in the low voltage distribution level where the compensating current could be high. Therefore multiple units can operate in parallel. This can be controlled in an active load sharing mode (intercommunication is required) or in droop control mode. The most important part is the common DC link between the APF units. Therefore, a circulating current could flow. In the case of a hysteresis current controller based multiple units in load sharing mode, this CC control is not yet achieved. One of the difficulties of this CC flow control or reduction is the variable switching frequency of the units. By proper selection of design parameters, this CC flow can be reduced in an acceptable level.

#### References

- S. K. Khadem, M. Basu, and M. F. Conlon, “A review of parallel operation of active power filters in the distributed generation system,” in
*Proceedings of the 14th European Conference on Power Electronics and Applications (EPE '11)*, pp. 1–10, September 2011. View at Scopus - S. K. Khadem, M. Basu, and M. F. Conlon, “Parallel operation of inverters and active power filters in distributed generation system—a review,”
*Renewable and Sustainable Energy Reviews*, vol. 15, no. 9, pp. 5155–5168, 2011. View at Publisher · View at Google Scholar · View at Scopus - H. Akagi and K. Nabae, “Control strategy of active power filters using multiple voltage source PWM converters,”
*IEEE Transactions on Industry Applications*, vol. 1, no. 3, pp. 460–466, 1985. View at Publisher · View at Google Scholar - L. Asiminoaei, E. Aeloiza, J. H. Kim et al., “Parallel interleaved inverters for reactive power and harmonic compensation,” in
*Proceedings of the 37th IEEE Power Electronics Specialists Conference (PESC '06)*, pp. 1–7, June 2006. View at Publisher · View at Google Scholar · View at Scopus - L. Asiminoaei, C. Lascu, F. Blaabjerg, and I. Boldea, “Performance improvement of shunt active power filter with dual parallel topology,”
*IEEE Transactions on Power Electronics*, vol. 22, no. 1, pp. 247–259, 2007. View at Publisher · View at Google Scholar · View at Scopus - Z. Ye, D. Boroyevich, J.-Y. Choi, and F. C. Lee, “Control of circulating current in parallel three-phase boost rectifiers,” in
*Proceedings of the 15th Annual IEEE Applied Power Electronics Conference and Exposition (APEC '00)*, pp. 506–512, February 2000. View at Scopus - T.-P. Chen, “Circulating zero-sequence current control of parallel three-phase inverters,”
*IEE Proceedings: Electric Power Applications*, vol. 153, no. 2, pp. 282–288, 2006. View at Publisher · View at Google Scholar · View at Scopus - M. Pattnaik and D. Kastha, “Harmonic compensation with zero-sequence load voltage control in a speed-sensorless DFIG-based stand-alone VSCF generating system,”
*IEEE Transactions on Industrial Electronics*, vol. 60, no. 12, pp. 5506–5514, 2013. View at Publisher · View at Google Scholar - C.-T. Pan and Y.-H. Liao, “Modeling and coordinate control of circulating currents in parallel three-phase boost rectifiers,”
*IEEE Transactions on Industrial Electronics*, vol. 54, no. 2, pp. 825–838, 2007. View at Publisher · View at Google Scholar · View at Scopus - T.-P. Chen, “Zero-sequence circulating current reduction method for parallel HEPWM inverters between AC bus and DC bus,”
*IEEE Transactions on Industrial Electronics*, vol. 59, no. 1, pp. 290–300, 2012. View at Publisher · View at Google Scholar · View at Scopus - L. Asiminoaei, E. Aeloiza, P. N. Enjeti, and F. Blaabjerg, “Shunt active-power-filter topology based on parallel interleaved inverters,”
*IEEE Transactions on Industrial Electronics*, vol. 55, no. 3, pp. 1175–1189, 2008. View at Publisher · View at Google Scholar · View at Scopus - S. K. Khadem,
*Power quality improvement of distributed generation integrated network with unified power quality conditioner [Ph.D. thesis]*, The Dublin Institute of Technology, Dublin, Ireland, 2013. - S. K. Khadem, M. Basu, and M. F. Conlon, “Harmonic power compensation capacity of shunt APF and its relationship to design parameters,”
*IET Power Electronics*. In press. - M. K. Mishra and K. Karthikeyan, “An investigation on design and switching dynamics of a voltage source inverter to compensate unbalanced and nonlinear loads,”
*IEEE Transactions on Industrial Electronics*, vol. 56, no. 8, pp. 2802–2810, 2009. View at Publisher · View at Google Scholar · View at Scopus - P. Venne, J. N. Paquin, and J. Bélanger, “The what, where and why of real-time simulation,” in
*Proceedings of the IEEE Power & Energy Society General Meeting (PES '10)*, pp. 37–49, 2010.