Research Article  Open Access
Mohammad Reza Miveh, Mohd Fadli Rahmat, Mohd Wazir Mustafa, Ali Asghar Ghadimi, Alireza Rezvani, "An Improved Control Strategy for a FourLeg GridForming Power Converter under Unbalanced Load Conditions", Advances in Power Electronics, vol. 2016, Article ID 9123747, 14 pages, 2016. https://doi.org/10.1155/2016/9123747
An Improved Control Strategy for a FourLeg GridForming Power Converter under Unbalanced Load Conditions
Abstract
This paper proposes an improved multiloop control strategy for a threephase fourleg voltage source inverter (VSI) operating with highly unbalanced loads in an autonomous distribution network. The main objective is to balance the output voltages of the fourleg inverter under unbalanced load conditions. The proposed control strategy consists of a proportionalintegral (PI) voltage controller and a proportional current loop in each phase. The voltage controller and the current control loop are, respectively, used to regulate the instantaneous output voltage and generate the pulse width modulation (PWM) voltage command with zero steadystate tracking error and fast transient response. A voltage decoupling feedforward path is also used to enhance the system robustness. Since the outer voltage loop operates in the synchronous reference frame, tuning and stability analysis of the PI controller is far from being straightforward. In order to cope with this challenge, the stationary reference frame equivalent of the voltage controller in the rotating frame is derived. Subsequently, a systematic design based on a frequency response approach is provided. Simulation results are also carried out using the DIgSILENT PowerFactory software to verify the effectiveness of the suggested control strategy.
1. Introduction
Poor operational efficiency, gradual depletion of fossilfuel resources, and environmental pollution are the main problems associated with traditional power systems [1–3]. These serious issues have led to a considerable attempt to generate power using renewable energy sources (RES) at the low voltage level [4, 5]. For applications in renewable energy and distributed generation (DG), there is a need to use power electronic inverters to convert DC power into a controlled AC power [6]. Conventionally, the inverters used in distribution networks behave like voltage sources when they operate independently [7]. On the other hand, they behave as current sources, when they are directly connected to the utility grid [8]. The change of operational mode from autonomous mode to gridconnected mode or vice versa may cause the change of their controllers’ scheme. The most important distinguishing feature of a voltage source inverter (VSI) is that there is no need to change its controller, when the operation mode is changed [7]. Therefore, it is commonly used in distribution networks, due to its proper capability to operate in both gridconnected and islanded modes [8]. Here, the autonomous operation of VSIs is considered. However, to achieve a stable and secure operation, a number of technical and regulatory issues have to be resolved before VSIs can become commonplace in distribution networks.
Since most traditional sixswitch inverters are designed for threephase threewire systems, their controllers are quite suitable for balanced threephase loads. In many low voltage distribution systems, the loads can be a mixture of singlephase and threephase ones, resulting in unbalanced voltage problems [9]. Unbalance voltage conditions can lead to adverse effects on equipment and the electric distribution system [10]. Malfunction of protection devices, power electronic converters, and adjustable speed drives are the main challenges caused by unbalanced loads in distribution networks [9, 10]. To cope with this challenge, a neutral line is needed to provide a current path for unbalanced loads in a threephase fourwire system. Hence, it is important to use a proper inverter topology to balance the output voltages of critical loads.
So far, various VSI topologies are introduced for proper operation in a threephase fourwire distribution network. The use of a threeleg inverter topology in threephase fourwire systems with a costly and bulky ΔY transformer is popular due to trapping zero sequence currents in the Δ winding. In this topology, the control of the inverter is only responsible for compensating the voltage drops caused by positive and negative sequence currents on the output filter of the inverter in the Δ side of the transformer. Nonetheless, the zero sequence currents may cause voltage drops in the Yside of the transformer that the threeleg inverter cannot handle this challenge [11]. The threeleg inverter with a split DClink capacitor has also been extensively used in the literature because of its simple structure [12, 13]. However, it needs an expensive and a large capacitor to achieve equal voltage sharing between the split capacitors. Moreover, capacitor voltage balancing is another challenge with this topology [14]. The threephase fourleg VSI plays an important role in the proper operation of threephase fourwire distribution networks because of its superior performance characteristics in handling unbalanced conditions. The provision of the fourth leg in fourleg VSIs can result in controlling the phase voltages independently. Indeed, the independently controlled phase voltages allow fourleg inverters to provide balanced output voltages even under unbalance load conditions.
To date, various control methods have been proposed in the literature to balance the output voltage of a threephase fourleg VSI in autonomous mode. The proportionalresonant (PR) controller in the stationary reference frame has been commonly used for balancing the output voltage of the fourleg inverter due to its superior performance in eliminating the steadystate error, while regulating sinusoidal signals [17]. However, it is sensitive to frequency variations and the phase shift of current sensors. The proportionalintegral (PI) controller in the frame is also widely used and works well with pure DC signals [15, 16, 18, 19]. This approach operates based on the extraction of the symmetrical components of the unbalanced signals in the frame. Nonetheless, the use of filters to obtain the symmetrical components of the unbalanced signals leads to low crossover frequency, which may cause a slow dynamic response. In another approach, a combination of the frame and the stationary reference frame is utilized to compensate distorting effects of nonlinear and unbalanced loads in a standalone distribution system [20]. The integral controllers in the frame are responsible for compensating the positive and negative sequence distortions, while a zerodamping bandpass filter is employed in the stationary reference frame to compensate the zero sequence distortion. However, the effectiveness of the proposed scheme is only presented for the steadystate condition, and the zero steadystate error for the zero sequence component is not truly achieved.
In this paper, an improved perphase control scheme for a threephase fourleg VSI operating with highly unbalanced loads in an autonomous distribution network is presented. The main objective is to effectively balance the output voltages of the fourleg inverter under extremely unbalanced load conditions. The proposed control strategy consists of an outer voltage loop and an inner current loop in each phase. The outer voltage controller and the inner capacitor loop are, respectively, utilized to regulate the instantaneous output voltage and currents. A voltage decoupling feedforward is also used to improve the system robustness. The main advantages of the method are the simplicity, low steadystate voltage tracking error, and fast transient response.
The rest of this paper is organized as follows. Section 2 describes the model of the fourleg inverter. Section 3 presents the proposed perphase multiloop control of the fourleg inverter in the frame. The stationary reference frame equivalent model of the PI controller in the synchronous reference frame is derived in Section 4. The design of the current loop and the voltage control are presented in Sections 5 and 6, respectively. The carrierbased pulse width modulation (PWM) method for the generation of the inverter output voltages is also explained in Section 7. Simulation results are provided in Section 8. Finally, the conclusion gives a brief summary and critique of the findings.
2. System Modeling
Figure 1 shows the power stage of a fourleg gridforming inverter and its LC output filter connected to unbalanced loads in an autonomous threephase fourwire distribution network [21]. Since the LC filter yields better performance than the L filter and is less complicated than the LCL filter, the LC filter represents a suitable compromise for the system intended for use in this paper. The LC filter parameters are chosen such that the unwanted components in the fourleg inverter output voltage are attenuated effectively and the inverter current ripple is reduced admissibly using the method presented in [17]. The loads can be placed either in linetoline or linetoneutral connection. It is worth noting that the neutral line of the autonomous fourwire system is provided by connecting the fourth legs of the fourleg inverter to the neutral point of loads. The additional leg regulates the load zero sequence voltage [22]. To minimize the switching frequency ripple imposed on the neutral current inverter (), a neutral inductor () is also used.
The carrierbased pulse width modulation (PWM) technique is selected to produce three output voltages independently because of its simplicity and ease of implementation [23]. Since the fourleg inverter is assumed to be powered by an ideal constant DC voltage source, no controller is needed to regulate the DClink voltage, and it is possible to consider that the DClink voltage is constant throughout this study [5]. Table 1 presents the parameters of the fourleg VSI.

To describe the behavior of the circuit depicted in Figure 1, the following quantities for voltages and currents can be defined:where is the vector of threephase inverter output linetoneutral PWM voltages.By applying Kirchhoff voltage and current laws to the power stage of the threephase fourleg VSI, the following equations can be obtained [21]. The control system tuning and stability analysis of the fourleg inverter can be performed on a perphase basis [7]. Hence, the power stage of the fourleg inverter is modeled according to the principles of the perphase basis so that only a singlephase representation of the inverter is used for the analysis and design [9]. Figure 2 illustrates the perphase representation of the fourleg inverter for one phase to neutral connection [2, 9]. As can be seen, the fundamental component of the switched voltage of each phase and the connected load to that phase are modeled as an ideal controlled voltage source (, which is the control variable) and a current source (), respectively. In this figure, and are also the respective phase inductor current and capacitor voltage, respectively.
For implementation of a singlephase system in the synchronous reference frame, it is necessary to generate a pseudotwophase system [2]. In this twophase system, one component is obtained from the original singlephase system () and an orthogonal signal () must be created from the original singlephase signal. Based on Figure 2, the differential equations representing the model of the singlephase system in the frame can be written asThe average switching model of the fourleg VSI in each phase is depicted in Figure 3. This is obtained by assuming that the switching frequency is much higher than the fundamental frequency. As can be seen from Figure 3, (the function of modulating signal) is used instead of the control variable, which represents the average value of over one cycle of switching frequency.
3. PerPhase Control Scheme
The independently controlled phase voltages allow the fourleg inverter to provide balanced output voltages under highly unbalanced load conditions. The perphase control scheme is used in this paper due to its superior performance in providing balanced output voltages under extremely unbalanced load conditions. In this control scheme, three legs are switched independently from each other so that voltages can be regulated in their output filter capacitors. The fourth leg of the inverter provides a zero voltage at the neutral point of the inverter using the proposed controller and carrierbased PWM technique [23].
The implementation of the independent control of the singlephase system in the frame needs to create a secondary orthogonal signal from each original phase signal through a complex orthogonal signal generation (OSG) technique [5]. Several attempts have been made in the literature to generate an orthogonal signal from an original singlephase signal such as secondorder generalized integrator, Kalman filter, and firstorder allpass filter (APF) methods [24–27]. In this paper, the orthogonal signal is generated based on the reference values of the  and axes [28, 29]. The proposed method exhibits improved steadystate and dynamic performances in comparison with the inverters equipped with the conventional orthogonal signal generation techniques.
The structure of the suggested control scheme for phase “” is presented in Figure 4. The control system consists of an inner current loop and an outer voltage loop in each phase. The main function of the external voltage loop is to control the instantaneous output voltages within the standard limits. The inner current loop is also adopted to generate the switching states of the PWM modulator. In addition, it improves the transient and steadystate performances of the proposed control scheme. A voltage decoupling feedforward is also used to enhance the control system robustness [2]. It is noteworthy that the capacitor current is employed as the feedback signal in the inner loop due to its superior performance in rejecting disturbances rather than the inductor current. Furthermore, the use of the capacitor current is much easier and more costeffective than the inductor current. According to the basic principles of control theory of cascaded control, these loops can be designed independently as long as the dynamics of the voltage loop is designed to be slower than the internal current controller [2].
The voltage loop operates in the synchronous reference frame, whereas the inner current loop functions in the stationary coordinate system. In the outer loop, is the phase output voltage of the filter capacitor to the neutral line. and are the real and the orthogonal components of in the stationary reference frame, respectively. The components of the phase output voltage of the filter capacitor can be generated by applying the Park transformation, after creating the pseudotwophase system. A simple phase locked loop (PLL) is used to obtain the and terms [30]. The PI controllers are utilized in the voltage loop to regulate the instantaneous output voltages in the frame. The reference voltages for the three phases have equal amplitudes but are separated from the other voltages by a phase angle of 120°. The component of the reference voltages in each phase () is set at 0, whereas the component () is set at the peak value of the reference phase voltage.
The reference signal of the internal current loop is provided by employing the inverse Park transformation to the output signals of the output voltage controller. As shown in Figure 4, only the axis quantity generated by the outer voltage loop is fed to the internal current controller for compensation. It is the real signal of the twophase system. Afterwards, the inner loop generates the switching states of the PWM using a simple proportional controller. The design approach of the proposed control strategy is discussed in detail in the following sections.
4. Stationary Reference Frame Representation of the PI Controller in the Frame
In the proposed control strategy, the PI controller regulates the instantaneous output voltages of the inverter in the synchronous reference frame, whereas the simple proportional controller regulates the current in the stationary reference frame. Hence, the stability analysis and design of the whole closedloop system is not straightforward. To successfully cope with this challenge, the stationary frame equivalent model of the PI controller is derived in this section [26, 27]. The equivalent model of the used PI controller in the stationary reference frame is depicted in Figure 5. In this block, stands for outputs, whereas stands for inputs. The is the transfer function of the proportional gain , and is the transfer function of the integral controller .
The equivalent model of the PI controller depicted in Figure 5 can be considered as a twoinputtwooutput system. It can be explained in the time domain aswhere is the convolution operator.
The Laplace transformation is used for both sides of (5). After some mathematical manipulation it can be written asIn (6), can be replaced by . After performing some mathematical manipulation this yieldsLastly, the transfer function of the real reference current to the real voltage error by replacing can be obtained aswhere , , , and .
is the stationary reference frame representation of the PI controller in the frame. Figure 6 shows the Bode plot of transfer function for a typical controller in rad/s. From this figure, it can be concluded that for fundamental frequency, the phase and amplitude characteristics of the PI controller in the frame are equivalent to the PR controller in the stationary reference frame. The use of this technique considerably simplifies the stability analysis and control parameter design.
5. Design of the Current Controller
The block diagram of the inner current loop is presented in Figure 7. A simple proportional controller is used for injecting clean current to the PWM [28, 29]. In spite of the complex structure of the PI compensator, the proportional controller provides more simplicity for the stability analysis and control parameter design. Moreover, it can prevent unwanted phase delays from the reference signal [5]. However, the use of the proportional controller in the internal loop requires a high proportional gain to eliminate the steadystate error. To successfully overcome this challenge, a feedforward path is adopted to simultaneously improve the performance of the inner loop and reduce the required control effort.
Since it can be assumed that is the load impedance and , the closedloop transfer function of the inner loop can be written asIt is obvious that the performance of the internal controller significantly depends on the load impedance and controller parameters. The Bode plot of the corresponding transfer function with a typical value for the proportional compensator in different loading conditions is shown in Figure 8.
It can be seen that the minimum bandwidth can be achieved at the nominal load. Hence, the proportional gain of the current controller must be tuned under nominal loading conditions to ensure the expected bandwidth in the inner loop. The proportional gain value of the current loop can be calculated using and assuming that is the required bandwidth of the inner loop. Hence, the proportional gain can be obtained asBasically, the required bandwidth must be selected lower than the switching frequency to put a limit on the inner loop response to the switching noise. Hence, it is chosen as onefourth of the switching frequency. From (10) and with , the proportional gain of the inner current loop is set on 1.
6. Design of the Voltage Controller
The next step after determining the gain of the inner loop is to design the outer voltage loop. The block diagram of the cascaded controller and its simplified block diagram are illustrated in Figure 9. In this figure, the internal controller and the external loop are, respectively, replaced by and . Moreover, is the voltage decoupling feedforward to enhance the system robustness. The Bode plots of the openloop transfer function of the simplified block diagram for , , and under different loading conditions are depicted in Figure 10. The effect of various loading conditions on the outer loop performance can be investigated from this figure. It can be observed that the stability of the closedloop system and the phase margin under lightload or noload conditions are moderately decreased.
(a)
(b)
To guarantee the proper performance of the inverter in all load conditions, the PI regulator is designed under lightload conditions. Since, under lightload conditions, the load impedance tends to infinity (, the transfer function of (9) can be approximated asAdditionally, by assuming that the inverter operates under the lightload condition, the openloop and closedloop transfer functions of the control system can be written as (12) and (13), respectively:In the PI controller, the proportional gain and the integral parameter should be accurately selected to ensure a fast transient response and zero tracking steadystate error. The selection of the proportional gain is a compromise between the stability of the controller and the desired voltage regulation bandwidth. In this study, the proportional gain is chosen so that the required bandwidth ( can be achieved for (13). On the other hand, the integral gain is chosen so that the minimum steadystate error for the outer loop can be ensured. In this case, the selection of the proportional parameter is performed based on this assumption that the dynamic of the voltage loop is unaffected by the integral gain. In other words, the proportional gain is responsible for the transient response, whereas the steadystate response is determined by the integral parameter at the fundamental frequency. Hence, it can be assumed that , during tuning the proportional parameter. Based on this assumption, the transfer function of the closedloop system in the frequency domain and under lightload condition can be rewritten asAssuming that the expected bandwidth is , can be obtained asIn practice, in order to achieve a satisfactory tradeoff between the disturbance rejection and the proper transient response in inverter applications, the system bandwidth must be selected between ten times of the fundamental frequency and onetenth of the switching frequency. In this study, it is chosen as 550 Hz, which is a value between 600 Hz and 500 Hz. Consequently, the system bandwidth and the proportional gain can be determined as Hz 3 krad/s and 0.15, respectively. The next step is to determine the integrator gain of the PI controller. The stability analysis is used to achieve an accurate value for integral parameter. The use of the RouthHurwitz criterion can be satisfied by the integrator objectives in the voltage loop. The system characteristic polynomial can be written asBy applying the RouthHurwitz criterion, the system stability analysis can discriminate as The proportional gain of the PI controller has been already determined. Therefore, the value of can be calculated equal to 55. To evaluate the performance of the system stability, the openloop Bode plots of for different values of are depicted in Figure 11. What is interesting in this figure is that has no effect on the phase margin. It is noteworthy that an infinitive magnitude at the fundamental frequency provides a zero steadystate error. However, it has a considerable influence on the operation of the controller in the area near the fundamental frequency. Additionally, based on the stationary reference frame equivalent of the integral term in Figure 6, which affects the system performance in vicinity of the fundamental frequency, the integral gain should be minimized to ensure that the integral term does not affect other frequencies. Indeed, this gain should be selected enough lower than the stability criterion in applications where variations of the fundamental frequency are expected, which may happen in the case of autonomous grids. Hence, the choice of should be done based on a tradeoff between eliminating the steadystate error and not affecting other frequencies. Based on this compromise and the RouthHurwitz criterion, is chosen to be 42.
7. The CarrierBased PWM Method for the Generation of the Inverter Output Voltage
Kim and Sul [23] propose a voltage modulation technique on the basis of a triangular carrier wave for threephase fourleg VSIs to make three lines to neutral output voltages using an additional leg. In this modulation method, the concept of offset voltage is implemented using a single carrier. The method has a strong performance and can be implemented easily. Therefore, it is used in this study to generate the inverter output voltage.
The block diagram of the used PWM scheme is shown in Figure 12. In this figure, are the “” component generated by the proposed cascaded controller. stands for the fictive midpoint of the DC link, and is the offset voltage, which is calculated quite different from threephase threeleg VSI using (18). The output voltages of the fourleg inverter () and pertaining constraint can be obtained by (19) and (20). Moreover, the ONtimes of the upper switch of respective legs can be obtained as (21):where is the period of the triangular carrier.
8. Simulation Results
To validate the performance of the proposed control strategy, the test system of Figure 1 has been simulated in the DIgSILENT PowerFactory software. The fourleg VSI is equipped with the suggested control scheme. The types of loads are resistive, and other parameters of the system are presented in Table 2. Different simulation case studies under various load scenarios are carried out to determinate the effectiveness of both the steadystate and the transient performances of the suggested control scheme.

8.1. SteadyState Performance
The evaluation of the steadystate behavior of the proposed control strategy is made for a threephase balanced load ( Ω) and three various unbalanced load cases, including ( Ω, Ω, Ω), Ω, , and ( Ω, ).
8.1.1. With a ThreePhase Balanced Load
The purpose of this part is to investigate the steadystate performance of the suggested controller strategy when a threephase balanced load is connected to the fourleg VSI. The balanced load includes a resistor of 8 Ω for each phase. The threephase pole voltage references and the offset voltage reference are shown in Figure 13. It can be seen from this figure that the threephase fourleg VSI has the considerable ability to provide desired pole voltage references with the expected amplitude for the threephase balanced load.
The output waveforms of load voltages, load currents, and neutral current for the fourleg VSI for the balanced load are also depicted in Figure 14. The results indicate that the proposed control strategy is capable of regulating the fundamental component of the load voltage close to the desired peak for the balanced load.
8.1.2. With SinglePhase and ThreePhase Unbalanced Loads
In this part, the steadystate performance of the proposed control strategy for various unbalanced load cases, including ( Ω, Ω, Ω), ( Ω, ), and ( Ω, ) are investigated. The simulation results of load voltages and currents for these different unbalanced load scenarios are depicted in Figures 15–17. Since the control structure adopts separate controller for each phase, the unbalanced loads have no influence on the voltage controller performance, and the load voltages remain balanced. From these figures, it is apparent that the proposed control technique has a significant ability to provide balanced output voltages for the fourleg VSI even under extremely unbalanced load condition containing a singlephase load between the phase and neutral.
According to the IEEE standards, the voltage imbalance needs to be maintained low, below 2% for sensitive loads [30, 31]. The performance of the suggested multiloop control strategy has been compared with the conventional control scheme [15, 16], with the same specification for the inner and outer control loops. In order to evaluate the value of phase voltage unbalance rate (PVUR), the magnitudes of the fundamental components of the threephase voltages and the PVUR of all tested scenarios for both the conventional and the suggested control schemes are presented in Table 3. The results show that the load voltages can remain balanced in steadystate for both the conventional and the proposed control scheme at all tested conditions. Moreover, the value of the PVUR is maintained below 2% at all tested conditions for both control strategies. However, the steadystate performance of the suggested perphase control scheme is improved because of avoiding the use of slow filterbased symmetrical components calculators.

8.2. Transient Performance
In this part, the evaluation of the transient behavior of the proposed control strategy is made for a threephase unbalanced load ( Ω, Ω, and Ω). To verify the transient performance of the proposed voltage control strategy a step change in the components of voltage references in all phases of the fourleg inverter is applied and then returns to its initial voltage value (while keeping ).
For the phase a step change from 155.56 to 75 V (peak) at 26 ms is applied and then returns to its initial voltage value at 79 ms. The transient behaviors of the voltage reference and the actual voltage of the respective phase are shown in Figure 18. The reference voltage (peak) value in phase “” is step changed from 155.56 to 140 V (peak) at 39 ms, afterwards back to 155.56 V at 79 ms. Figure 19 also depicts the transient response of the voltage reference and the actual voltage of the phase.
For the phase also a step change from 155.56 to 135 V (peak) at 46 ms is applied and then returns to its initial voltage value at 79 ms. Figure 20 illustrates the waveforms of the voltage () reference and actual voltage of the pertaining phase. As can be seen, the voltage controllers in each phase demonstrate very fast dynamic, and the actual voltages are capable of following closely their references. The PI controllers take about 1 cycle to track reference voltage in each phase. It is apparent that the proposed controller can change the load voltages close to their references with very fast dynamic.
8.2.1. Comparison between the Conventional and the Proposed Control Scheme
In this part, the transient performance of the proposed control strategy has been compared with the conventional control scheme [15, 16], with the same specification for the voltage and current controller. In this simulation, while the threephase fourleg gridforming unit is initially supplying a balanced load (8 Ω/ph), a singlephase inductive load ( = 20 Ω and = 2 mH) is added between phases “” and “” at 0.3 s. After 0.2 s, the connected load between phase “” and neutral is changed from the nominal load to pure resistance of 5.7 Ω. Lastly, the nominal load between phase “” and neutral is disconnected at 0.7 s.
The output waveforms of load voltages under varying unbalanced load conditions are depicted in Figure 21, for both the conventional and the suggested control schemes. As can be seen, both control strategies can keep the load voltages balanced in steadystate under varying unbalanced load conditions. To compare the speed of response of two control schemes, the transient load voltages for both control strategies are provided with zoomed Figures. It can be seen that the load voltage waveforms are unaffected by the load transients in the proposed scheme. Comparing the two results, it can be seen that no significant changes in the load voltages can be observed with the proposed scheme. While there exist at least three line cycles transient with the conventional approach, the results show that the suggested controller has a significant ability to balance the output voltages under severe unbalanced load conditions with zero steadystate error and fast dynamic response.
(a)
(b)
9. Conclusion
In this study, a new perphase cascaded voltagecurrent control strategy for a threephase fourleg VSI operating with highly unbalanced loads in an autonomous distribution network is presented. The suggested control scheme provides balanced output voltages for the fourleg inverter even under extremely unbalanced loading conditions. It consists of an outer voltage loop in each phase to regulate the instantaneous output voltages and an inner current loop in each phase to improve both the steadystate and transient behaviors of the control system. The frequency response approach is used for tuning and stability analysis. The transient and steadystate performances of the suggested control scheme are investigated using simulation studies. The simulation results show that the suggested controller has a significant ability to balance the output voltages under severe unbalanced load conditions with zero steadystate error and fast dynamic response.
Competing Interests
The authors declare that they have no competing interests.
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Copyright © 2016 Mohammad Reza Miveh et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.