Abstract
A computer-aided topological hybrid layout-design procedure is proposed, that yields the wanted principal routing in the form of a geometrical planarization graph. A so-called grid-embedding of a circuit graph into the Euklidean plane enables us to observe all except one of the various technological constraints. The real problem is reduced to finding a proper arrangement of “nets” and “flocks” in the plane in order to meet the omitted cross-capacity constraint. The solution is accomplished by a constructive and implicit enumeration procedure, which is used within an interactive man-machine design process.