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ElectroComponent Science and Technology
Volume 9 (1981), Issue 1, Pages 3-8
http://dx.doi.org/10.1155/APEC.9.3

High Density Packaging Technology

Toshiba R & D Center, Toshiba Corporation, Japan

Copyright © 1981 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A chip and wire, high density packaging approach has resulted in a low cost, large scale, high density, multi-chip package (MCP). The package includes 76 ICs, 1 resistor, and 34 capacitor chips on a 2 in × 3 in multilayer ceramic substrate (MLS) with 92 I/O leads. The package has a solder-sealed, metal cover over the chip-mount area, and a heat sink on the back side of the MLS.

The primary yield was found to be around 70%. The rest was reworked with no significant labour. The software as well as hardware to minimize the test/rework labour would be a key to success in chip and wire MCPs. Also, efforts were made to reduce the material cost and the assembly labour. The thick film MLS was replaced by the ceramic MLS. The wire bonding was automated. Overall efforts reduced package cost to 1.25 times the conventional DIP-on-PCB counterpart (7.5 in × 9.1 in). Estimating its effectiveness at a system level, the reduction in the number of boards, connectors and cables would give MCPs an advantage over their counterparts. The improvement in reliability would be another advantage

A comparison with other high density packaging technologies, chip carrier, and chip on tape, is also described.