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Active and Passive Electronic Components
Volume 17, Issue 4, Pages 283-296

Simulation of Crosstalk in High-Speed Multi-Chip Modules

National Technical University of Athens, Division of Computer Science, Department of Electrical Engineering, Microelectronics Technology Group, Greece

Received 10 May 1993; Accepted 25 September 1993

Copyright © 1995 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Simulation results of the electrical performance at 1 GBits/sec of a number of different off-chip interconnection architectures are presented with emphasis given to the dependence of crosstalk and signal delay on the geometries and dielectric constants of the insulating layers as well as on the widths and separations of the conductors. The results indicate that signal delay and crosstalk may be reduced by using low εr values for the dielectrics and that crosstalk may be also reduced by reducing the conductor-to-ground wire separation which simultaneously neutralises the role of εr value on crosstalk and line impedance.