Simulation of Crosstalk in High-Speed Multi-Chip Modules

Abstract

Simulation results of the electrical performance at 1 GBits/sec of a number of different off-chip interconnection architectures are presented with emphasis given to the dependence of crosstalk and signal delay on the geometries and dielectric constants of the insulating layers as well as on the widths and separations of the conductors. The results indicate that signal delay and crosstalk may be reduced by using low εr values for the dielectrics and that crosstalk may be also reduced by reducing the conductor-to-ground wire separation which simultaneously neutralises the role of εr value on crosstalk and line impedance.