Abstract

In this paper a MMIC QPSK modulator is described. The bit rate of the baseband signal is 155 Mbits/sec, while the frequency of the carrier is fLO=10 GHz . The modulation is performed directly at the RF band and therefore an IF stage is not necessary. The design contains all the necessary sub-circuits except for the demultiplexer and the low-pass filters, which are used so that the bandwidth of the binary waves can be reduced. The mixers that are contained in the circuit are not the typical Gilbert cells and as a result they occupy a much smaller area (half). The circuit needs no external LO coupler and no RF chocks. The F-20 process of GEC Marconi was used for designing the modulator. The occupied area is approximately 12 mm2 . Section 1 presents fundamentals on Quadriphase Shift Keying (QPSK), while in Section 2 the characteristics of the F-20 process are described. In the following Sections the sub-circuits, the complete circuit, and its simulated results are presented.