Research Article | Open Access
Electronically Tunable Dual-Input Integrator Employing a Single CDBA and a Multiplier: Voltage Controlled Quadrature Oscillator Design
A new dual-input differential input active integrator using a current differencing buffered amplifier (CDBA) is proposed. A multiplier element is appropriately used in the circuit whose control voltage () tunes the integrator time constant () electronically. The design of a voltage controlled quadrature oscillator (VCQO) based on the proposed integrator had been satisfactorily implemented. A new type of measurement for the tuning error of the oscillator based on the Nyquist plot is presented that shows an error of only 2% at 1?MHz with Total Harmonic Distortion (THD) less than 3%.
With the advent of the CDBA building block [1, 2], various analog signal processing/conditioning circuit realisation schemes using this element appeared in the recent literature [2–6]. The CDBA offers several advantageous features viz., high slew rate, improved bandwidth, and accurate port tracking characteristics when configured with a pair of matched current feedback amplifier (AD-844-CFA) devices [3, 4] which leads to extremely low active circuit sensitivity. We propose here a new electronically tunable differential integrator using a CDBA; the control voltage of a multiplier element, incorporated suitably in the circuit, tunes electronically.
The ICL-8013 device is a four-quadrant analog multiplier whose output is proportional to the electronic product of two input voltage signals with a transmission constant [7, 8]. The high accuracy (±1%), relatively wide bandwidth (B = 1?MHz), and improved versatility make it quite suitable for analog signal conditioning and active filter design applications.
Albeit various CDBA-based active filters/oscillators [3–6] are now available, the feature of electronic tuning in the CDBA active function circuit had not yet been reported. The design of a voltage controlled quadrature oscillator (VCQO) had then been implemented using the double integrator loop. The proposed functions had been verified by PSPICE macromodel simulation of the AD-844 based CDBA and by hardware circuit tests.
The proposed circuit is shown in Figure 1. The nodal equations characterizing an ideal CDBA element are . Analysis with these port relations for the CDBA [1–4] and writing the multiplier [7, 8] output = where multiplier constant = 0.1 per volt  yield where denotes the shunt parasitic transadmittance at node of the CDBA; as per datasheet  mho and .
We therefore get the realisability conditions for a true differential integrator, putting ; to 4, as here we assumed . With (2) in (1), an ideal dual-input integrator function is obtained as where if then with Hence the time constant is electronically tunable for the range ?V d.c.
With a nonideal CDBA device, these design equations would alter. The device imperfections may be expressed in terms of some port mismatch ratios [2–4] given by the relations The and terminals of the CDBA however are internally grounded; hence In the literature, the mismatch ratios are postulated in terms of some low-magnitude error [2–6] quantities given by , and for an ideal device the errors vanish.
By Reanalysis assuming finite quantities, we get a modified transfer equation
The realisability conditions for a true differential integrator now modify to Here we neglect the error products since ; thus .
The active -sensitivity may be estimated after writing for simplicity, which gives since [4, 11, 12]. Effect of the multiplier device nonideality may be derived by expressing so that we can effectively write for sensitivity calculation, which yields
In this analysis, we neglected the parasitic series resistance (?ohm)  of the CDBA and noted that the -node parasitics are bypassed to ground since The integrator quality factor may be evaluated after writing and then deriving given by where
Inspection of (7) indicates the realisability of high quality integration where may be preset to a high value by , and sets the realisability while tunes electronically and independently. For example, if we assume for a desired at ?MHz with a typical set of values ?V d.c., ?nF, ?nF, and K, then from (7) we get ?K.
3. VCQO Design
The quadrature oscillator finds various applications in SSB modulators and spectral phase measurements: its functional capabilities are further enhanced if electronic tuning property can be incorporated. We design a VCQO using the proposed integrator in a two integrator loop, each being used single ended, one inverting and the other in noninverting mode, that is, from (3) we designed and , thereafter cascading the two integrators in a loop.
With identical integrator, the oscillation frequency would be . The frequency stability factor is evaluated by at where is loop phase shift. After putting we obtained since we selected . A comparison of the values with some recent CDBA based oscillators is listed in Table 1.
4. Simulation and Experimental Results
Both the integrator and VCQO functions have been tested with PSPICE macromodel simulation  and by breadboarding hardware circuit after implementing the CDBA block with a pair of AD-844 devices  being biased with ?V.d.c. regulated supply. The results are shown in Figure 2. The responses had been measured for a range of 150?KHz ?MHz with suitable set of RC components wherein ?V d.c. is used for the tunability range taking The ICL-8013 multiplier element is implemented through the Macromodel databook [7–9]. It may be mentioned here that one can select any of the two default values of the multiplier constant and for the ICL 8013 multiplier device [7–9, 13, 14] in order to enhance the tuning range concomitantly while keeping and as the limit.
(a) Integrator response with square wave excitation of V(peak) at 1 MHz using K.ohm, K.ohm, K.ohm, pF (measured) pF and V.d.c.
(b) VCQO-tuning characteristics with nF
(c) VCQO wave-response with build-up feature tuned for MHz
(d) Nyquist plot of loop function measured in the vicinity of with above keys. Nominal tuned frequency : A 1 MHz B 0.72 MHz C 0.5 MHz
(e) Frequency spectrum of the loop-function measured at the tuned frequency of 1 MHz
We tested the frequency response of the integrator with antiphase input sinusoid signals and observed the phase error of about 5.5° at 1?MHz. The CMRR had been measured to be 96?dB with sinusoid excitation. It may be seen that the select-frequency was reported in the range of a maximum of 200?KHz in the earlier circuits [3, 4, 6]. Embedding the HA 2557 multiplier device [7, 8] with BW 130?MHz, in place of the ICL-8013 BW(1?MHz), it is possible to obtain an extended frequency range.
In order to examine the tuning error in we had carried out a new type of measurement using the Nyquist plot of the loop transfer function of the double-integrator loop in the vicinity of as shown in Figure 2(d). The deviation is then computed from the intersection of the function with the real axis of the plot following the Barkhaussen criterion. We obtained three such graphs corresponding to oscillation generation at the nominal frequencies of 500?KHz, 720?KHz, and 1.02?MHz. The tuning error is then derived as shown in Figure 2(e) and Table 2.
A new single CDBA-based differential integrator with a multiplier element in the circuit loop is presented for obtaining electronic tunability. Subsequently, a double integrator type VCQO had been designed and tested in a frequency range of 150?KHz–1?MHz with suitable design. Albeit other electronically tuned active realisations were reported recently in relatively lower frequency-range using CFA , current conveyors [15, 16], or OTA-based allpass filter , such a function circuit using the CDBA had not yet been presented.
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