High-Input Impedance Voltage-Mode Multifunction Filter with Four Grounded Components and Only Two Plus-Type DDCCs

Abstract

This paper introduces a novel voltage-mode multifunction biquadratic filter with single input and four outputs using two plus-type differential difference current conveyors (DDCCs) and four grounded passive components. The filter can realize inverting highpass, inverting bandpass, noninverting lowpass, and noninverting bandpass filter responses, simultaneously. It still maintains the following advantages: (i) using grounded capacitors attractive for integration and absorbing shunt parasitic capacitance, (ii) using grounded resistors at all 𝑋 terminals of DDCCs suitable for the variations of filter parameters and absorbing series parasitic resistances at all 𝑋 terminals of DDCCs, (iii) high-input impedance good for cascadability, (iv) no need to change the filter topology, (v) no need to component-matching conditions, (vi) low active and passive sensitivity performances, and (vii) simpler configuration due to the use of plus-type DDCCs only. HSPICE and MATLAB simulations results are provided to demonstrate the theoretical analysis.

1. Introduction

As a current-mode active device, the differential difference current conveyor (DDCC) has the advantages of both the second-generation current conveyor (CCII) (such as large signal bandwidth, great linearity, wide dynamic range) and the differential difference amplifier (DDA) (such as high-input impedance and arithmetic operation capability) [1]. This element is a versatile building block whose applications exist in the literature [1–7]. Voltage-mode active filters with high-input impedance are of great interest because several cells of this kind can be directly connected for implementing higher-order filters [3–11]. In 2003, Chang and Chen proposed a universal voltage-mode filter with three inputs and a single output [2]. The circuit can realize all five different generic filtering responses but only highpass and bandpass responses have the advantage of high-input impedance. In 2004, Horng et al. proposed a multifunction filter with a single input and three outputs [3]. The circuit can realize highpass, bandpass, and lowpass responses, simultaneously. However, it is based on two minus-type DDCCs. In 2005, Ibrahim et al. proposed two single DDCC biquads with high-input impedance and minimum number of passive elements [4]. The highpass, bandpass, or lowpass filter responses cannot be realized in the same configuration. In 2007, Chiu and Horng proposed a universal voltage-mode filter with three inputs and a single output [5]. The circuit has high-input and low-output impedance advantages but it uses three plus-type DDCCs. In the same year, Chen proposed a universal voltage-mode filter based on two plus-type DDCCs [6]. The proposed configuration suffers from high-input impedance. Recently, Horng proposed another universal voltage-mode filter with three inputs and five outputs [7]. However, it still uses three plus-type DDCCs. In this paper, a new voltage-mode multifunction biquadratic circuit with single input and four outputs is presented. The proposed circuit employs only two plus-type DDCCs, two grounded capacitors, and two grounded resistors. It has the same advantages reported by Horng et al. [3], such as realization of highpass (HP), bandpass (BP), and lowpass (LP) filter responses from the same configuration, no requirements for component-matching conditions, the use of only grounded capacitors and resistors, high-input impedance, and low active and passive sensitivity performances. Moreover, the proposed circuit is simpler in configuration than the old circuit, since the use of only plus-type of DDCC is simpler than minus-type one like a CCII [11].

2. Circuit Description

The DDCC is a five-terminal analog building block and its terminal relations are given by 𝐼_𝑌1=𝐼_𝑌2=𝐼_𝑌3=0, 𝑉_𝑋=𝑉_𝑌1−𝑉_𝑌2+𝑉_𝑌3, and 𝐼_𝑍=𝐼_𝑋 [1]. The proposed multifunction biquadratic circuit comprises two plus-type DDCCs, two grounded capacitors, and two grounded resistors, as shown in Figure 1. The use of grounded capacitors makes the circuit suitable for integration because grounded capacitor circuit can compensate for the stay capacitances at their nodes [12, 13]. Derived by each nodal equation of the proposed, the input-output relationship matrix form of Figure 1 can be expressed as𝑠𝐶₁0−𝐺₁0𝐺₂𝑠𝐶₂𝑉001−1101001^𝑜1𝑉_𝑜2𝑉_𝑜3𝑉_𝑜4=00−𝑉_in0, (1) where 𝐺₁=1/𝑅₁ and 𝐺₂=1/𝑅₂.

Figure 1 

The proposed high-input impedance voltage-mode multifunction biquad based on plus-type DDCCs.

To derive (1), all the 𝑌₁, 𝑌₂, and 𝑌₃ terminals of DDCC are high-impedance terminals, since they are connected to gates of MOS devices in actual implementation, whereas the port 𝑋 is low-impedance terminal [1]. Similarly the port 𝑍+ also exhibits high impedance since it is connected to the output stage of current mirror. From (1), the following four output voltages can be derived as𝑉_𝑜1𝑉_in=−𝑠𝐶₂𝐺₁𝑠²𝐶₁𝐶₂+𝑠𝐶₂𝐺₁+𝐺₁𝐺₂,𝑉_𝑜2𝑉_in=𝐺₁𝐺₂𝑠²𝐶₁𝐶₂+𝑠𝐶₂𝐺₁+𝐺₁𝐺₂,𝑉_𝑜3𝑉_in=−𝑠²𝐶₁𝐶₂𝑠²𝐶₁𝐶₂+𝑠𝐶₂𝐺₁+𝐺₁𝐺₂,𝑉_𝑜4𝑉_in=𝑠𝐶₂𝐺₁𝑠²𝐶₁𝐶₂+𝑠𝐶₂𝐺₁+𝐺₁𝐺₂. (2)

Thus, we can obtain an inverting BP, a non-inverting LP, an inverting HP, and a non-inverting BP filter response at the output voltages; 𝑉_𝑜1, 𝑉_𝑜2, 𝑉_𝑜3, and 𝑉_𝑜4, respectively. In order to realize allpass and bandstop filter functions, the unity gain voltage difference amplifier is needed. Due to the fact that input voltage signal is connected directly to the 𝑌₂ port of the DDCC(1) and input current to the 𝑌₂ port is zero, the circuit has the feature of high-input impedance. The employs of only plus-type DDCCs simplify the circuit configuration.

The resonance angular frequency 𝜔_𝑜, quality factor 𝑄, and bandwidth BW are given by 𝜔_𝑜=1𝑅₁𝑅₂𝐶₁𝐶₂,𝑄=𝑅₁𝐶₁𝑅₂𝐶₂𝜔,BW=^𝑜𝑄=1𝑅₁𝐶₁. (3) Equation (3), the parameters 𝜔_𝑜, and BW can be orthogonally adjusted by resistor 𝑅₁ while the orthogonal tuning 𝜔_𝑜 and 𝑄 can be achieved by simultaneous adjustment of 𝑅₁ and 𝑅₂ such that 𝑅₁=𝑅₂. It must be noted that the use of grounded resistors in the proposed circuit will benefit by an easier electronic tunability. Thus, for the case of 𝑅₁=𝑅₂ can be solved by using two MOSFETs to replace 𝑅₁ and 𝑅₂ with its gate connected by the same voltage control [14, 15]. Several realizations of tunable grounded resistors exist in the literature [16, 17].

3. Effect of Nonidealities

Take into account the nonidealities of a DDCC, namely, 𝑉_𝑋=𝑅_𝑋𝐼_𝑋+𝛽𝑉_𝑌1−𝛾𝑉_𝑌2+𝜂𝑉_𝑌3 and 𝐼_𝑍=𝛼𝐼_𝑋, where 𝑅_𝑋, 𝛼, 𝛽, 𝜂, and 𝛾 are the intrinsic resistance at the 𝑋 terminal, the parasitic current gain at the 𝑋 terminal to the 𝑍 terminal, the parasitic voltage gain at the 𝑌₁ terminal to the 𝑋 terminal, the parasitic voltage gain at the 𝑌₂ terminal to the 𝑋 terminal, and the parasitic voltage gain at the 𝑌₃ terminal to the 𝑋 terminal, respectively. These parasitic components limit the high-frequency operation of the circuit and can be modeled with the following first-order functions [18]:𝛼𝛼=^𝑜1+𝜏_𝛼𝑠,𝛽𝛽=^𝑜1+𝜏_𝛽𝑠,𝛾𝛾=^𝑜1+𝜏_𝛾𝑠,𝜂𝜂=^𝑜1+𝜏_𝜂𝑠. (4)

In (4), the pole frequencies 𝜔_𝛼=1/𝜏_𝛼, 𝜔_𝛽=1/𝜏_𝛽, 𝜔_𝛾=1/𝜏_𝛾, and 𝜔_𝜂=1/𝜏_𝜂 depend on the technological parameters and ideally approach infinity. The operation frequency of the presented filter can be defined as 𝑓≪min{𝜔_𝛼,𝜔_𝛽,𝜔_𝛾,𝜔_𝜂}. In addition, the dc gain 𝛼_𝑜, 𝛽_𝑜, 𝛾_𝑜, and 𝜂_𝑜 are ideally equal to unity and can be expressed as 𝛼_𝑜=1−𝜀_𝛼, 𝛽_𝑜=1−𝜀_𝛽, 𝛾_𝑜=1−𝜀_𝛾, and 𝜂_𝑜=1−𝜀_𝜂, where 𝜀_𝛽, 𝜀_𝛾, and 𝜀_𝜂 are the voltage tracking errors, and 𝜀_𝛼 is the current tracking error in addition to|𝜀_𝛽|≪1, |𝜀_𝛾|≪1, |𝜀_𝜂|≪1, and |𝜀_𝛼|≪1. Taking into account the nonidealities, the denominator of the transfer functions of Figure 1 becomes𝐷(𝑠)=𝑠²𝐶₁𝐶₂+𝛼_𝑜1𝜂_𝑜1𝛾_𝑜2𝑠𝐶₂𝐺^′₁+𝛼_𝑜1𝛼_𝑜2𝛽_𝑜1𝛾_𝑜2𝐺^′₁𝐺^′₂. (5) The nonideal resonance angular frequency 𝜔_𝑜 and quality factor Q are obtained by𝜔₀=𝛼_𝑜1𝛼_𝑜2𝛽_𝑜1𝛾_𝑜2𝐺^′₁𝐺^′₂𝐶₁𝐶₂1,𝑄=𝜂_𝑜1𝛼_𝑜2𝛽_𝑜1𝐶₁𝐺^′₂𝛼_𝑜1𝛾_𝑜2𝐶₂𝐺^′₁. (6)

A sensitivity study forms an important index of the performance of any active network. The formal definition of sensitivity is 𝑆^𝐹_𝑥=(𝑥/𝐹)(𝜕𝐹/𝜕𝑥), where F represents one of 𝜔_o, 𝑄 and 𝑥 represents any of the elements (𝐺^′₁−𝐺^′₂, 𝐶₁−𝐶₂) or the active parameters (𝛼_i, 𝛽_i, 𝛾_i, 𝜂_i). Based on the sensitivity expression, the active and passive sensitivities of the proposed circuit shown in Figure 1 are given as𝑆^𝜔𝑜_{𝛼𝑜1,𝛼𝑜2,𝛽𝑜1,𝛾𝑜2}=𝑆^𝜔𝑜_{𝐺′1,𝐺′2}=−𝑆^𝜔𝑜_𝐶1,𝐶2=12,𝑆^𝑄_{𝛼𝑜2,𝛽𝑜1}=𝑆^𝑄_{𝐶1,𝐺′2}=−𝑆^𝑄_{𝛼𝑜1,𝛾𝑜2}=−𝑆^𝑄_{𝐶2,𝐺′1}=12,S^Q_𝜂o1=−1. (7) Hence, the filter parameter sensitivities are low and not larger than unity in absolute value.

4. Simulation Results

The device model parameters used for the HSPICE simulations are TSMC 0.35 𝜇m CMOS 2P4M process and MATLAB for the theoretical part to compare the results. The CMOS implementation of the differential difference voltage current conveyor is shown in Figure 2 [4]. The NMOS and PMOS transistor aspect ratios are given by 𝑊/𝐿=2.5 𝜇m/0.5 𝜇m and 𝑊/𝐿=10 𝜇m/0.5 𝜇m, respectively. The supply voltages are 𝑉_DD=−𝑉_SS=1.65 V, and the biasing voltages of 𝑉_𝑏1 and 𝑉_𝑏2 are −0.1 V and −0.8 V, respectively. The proposed circuit was designed for 𝑓_𝑜=1 MHz and 𝑄=1 by choosing 𝑅₁=𝑅₂=50 kΩ and 𝐶₁=𝐶₂=3.18 pF. Figure 3 shows the simulated results amplitudes for HP, LP, and two BP filter responses of Figure 1. The total power dissipation is found to be 0.52 mW. As can be seen, there is a close agreement between theory and simulation.

Figure 2 

CMOS implementation of the plus-type DDCC.

Figure 3 

Simulated frequency responses of highpass, bandpass, and lowpass of Figure 1 at 𝑓𝑜=1 MHz and 𝑄=1.

The noise behavior of the filter was simulated using the INOISE and ONOISE statements of frequency responses of the BP response at 𝑉_𝑜4 output terminal. Figure 4 shows the simulated amplitude-frequency responses for the BP filter with INOISE- and ONOISE-designed 𝑅₁=𝑅₂=31.8 kΩ and 𝐶₁=𝐶₂=5 pF. The total equivalent input and output noise voltages are 13.8 mV and 0.48 mV, respectively.

Figure 4 

Equivalent output and input noise of the bandpass filter versus frequency.

To test the input dynamic range of the filter, the simulation has been repeated for a sinusoidal input signal at 𝑓_𝑜=1 MH_Z. Figure 5 shows the input dynamic range of the inverting BP response at 𝑉_𝑜1 output terminal with 𝑅₁=𝑅₂=50 kΩ and 𝐶₁=𝐶₂=3.18 pF, which extends up to amplitude of 0.7 V (peak to peak) without signification distortion. The dependence of the output harmonic distortion of BP filter on input voltage amplitude is illustrated in Figure 6. From Figure 6, we can see that the harmonic distortion rapidly increases if the input signal is increased beyond 0.7 V for the chosen DDCC implementation.

Figure 5 

The input and output waveforms of inverting BP response for a 1 MHz sinusoidal input of 0.7 V (peak to peak).

Figure 6 

THD variations of the BP filter versus amplitudes of the applied sinusoidal voltages at 1 MHz.

5. Conclusion

In this paper, the author also proposes a new high-input impedance voltage-mode multifunction biquadratic filter. This circuit offers several advantages, such as no requirements for component-matching conditions, the use of only grounded passive components, high-input impedance, and low active and passive sensitivity performances. The proposed circuit has the same advantages reported by [3] which is using two minus-type DDCCs, two grounded capacitors, and two grounded resistors. Moreover, the proposed circuit is simpler in configuration than the old circuit, since the use of only plus-type of DDCCs is simpler than the use of the minus-type of DDCCs. In addition to inverting highpass, inverting bandpass, and non-inverting lowpass filter responses, the proposed circuit can also realize non-inverting bandpass filter response.

Acknowledgments

The author would like to thank National Chip Implementation Center (CIC) for technical support. The work was sponsored by NSC-98-2221-E-131-027.