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Active and Passive Electronic Components
Volume 2010, Article ID 542406, 11 pages
Research Article

Transition Frequencies and Negative Resistance of Inductively Terminated CMOS Buffer Cell and Application in MMW LC VCO

Center for Research in Analog & VLSI Microsystem dEsign (CRAVE), School of Engineering and Advanced Technology (SEAT), Massey University, Albany, Auckland 0632, New Zealand

Received 31 May 2010; Revised 18 August 2010; Accepted 6 October 2010

Academic Editor: M. A. Do

Copyright © 2010 S. M. Rezaul Hasan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper investigates the transition frequencies () of an inductively terminated CMOS source follower buffer for negative resistance behavior at which the effective shunt resistance looking into the source of the buffer cell changes sign. Possible limiting frequencies of oscillation are determined based on resonators formed by a grounded gate inductor and a parasitic capacitance at the gate of the negative resistance buffer cell. The range of frequencies of oscillation of this negative resistance buffer cell for variations in the different circuit parameters/elements is explored. Following this, a millimeter wave (MMW) oscillator is simulated using the IBM 130 nm CMOS process technology which can operate at 70 GHz. High-frequency MOSFET model was used for these simulations. The cell had an extremely low power dissipation of under 3 mW. Extensive Monte Carlo simulations were carried out for manufacturability analysis considering up to 50% variation in process and geometrical parameters, supply voltage, and ambient temperature. Noise analysis and a simulated estimate of the phase noise in an MMW LC VCO application is also reported.

1. Introduction

Developing cost-effective advanced microwave communication systems using Millimeter wave (MMW) oscillators, or MMW voltage controlled oscillators (VCOs) on low-cost nanometric bulk CMOS process technologies is of immense interest in the semiconductor and circuit design research community. Design of MMW Oscillators and VCOs in III-V compound semiconductors and Si-Ge Heterojunction devices [14] has been reported for many years, but in recent times vast effort has been focused on CMOS MMW implementations [58]. In this regard, investigation of the high-frequency behavior and maximum possible oscillation frequency of CMOS negative resistance cell is crucial as CMOS devices have inherently lower unity-gain frequency () compared to III-V compound semiconductor FET and Si-Ge HBT devices. Recently Veenstra and van der Heijden [9] proposed the maximum possible oscillation frequency of a negative resistance cell as , which is defined as a frequency where the effective negative resistance of the cell turns from negative to positive. The well known cross-coupled CMOS negative resistance cell has the disadvantage of a which is hard-limited by device size and bias drain. CMOS imitations of cross-coupled and other bipolar cells to overcome these limitations has been largely unsuccessful [7]. On the other hand, CMOS versions of Colpitts and Clapp (or Clapp-Gouriet) oscillators were found to have higher than a cross-coupled CMOS pair but suffers from severe deterioration of with output loading at the drain node, and, needed a critical output buffer stage. Recently, the authors in [7] suggested an LC degenerated negative resistance cell to extend considerably the into the 100 GHz MMW range. The was found to be bounded by where and constitute the source degeneration. In this paper we further investigate to reach the ultimate boundary of  GHz MMW range of a CMOS negative resistance cell and propose a parasitic resonated CMOS negative resistance source follower buffer-cell using a gate inductor and a parasitic gate capacitance.

2. Transition Frequencies and Negative Resistance of CMOS Buffer Cell

Figure 1 shows the circuit diagram of an NMOS source follower Mb with gate and source inductors and an LC tank cascaded at the source for operation as LC VCO. The distributed gate resistance () is in series with the inductor and contributes to the -degradation of . However, is known to be lower than the base resistance of a bipolar device [10] and can be reduced considerably through a careful folded multifinger layout structure [11]. The source inductor works as a DC path and as an AC choke for the output AC signal connection to the tank (consisting of , and ). The transistor’s main parasitic capacitances reactive in RF operation are indicated with dotted lines, where, is the gate-to-source capacitance, is the drain-to-gate capacitance and is the source-to-body capacitance. Although the body of Mb is connected to ground, there is an AC body effect due to , charging and discharging . The main difference between this proposed circuit and that in [7] is that the tank circuit in the proposed design (being a common-drain configuration) is placed at the source terminal whereas that in [7] (being a common-source with source degeneration configuration) is placed at the drain terminal. The body (-substrate) is connected to the ground in both cases. Also, the is explored from the parallel combination of the gate inductor and the parasitic gate capacitance in the proposed buffer cell compared to the parallel combination of the source inductor and source capacitance in the design in [7]. Figure 2(a) shows the negative resistance buffer cell with the embedded small signal high-frequency equivalent circuit of the buffer device Mb, where is the transconductance and is the body transconductance of the buffer device. All other model components have their usual meaning for a hybrid- model. and are parasitic capacitances at the gate and the drain of Mb. In Figure 2(b) the embedded model is slightly simplified by setting (the drain access resistance) and (the equivalent nonquasi-static resistance) to be reasonably negligible [7, 12] resulting in and becoming terminated to AC ground at both ends. Next, in Figure 2(c) the body-effect transconductance current source () has been simplified into a simple conductance () since the voltage-dependent body-effect transconductance current source is due to a voltage across its own terminals for a common-drain configuration [13]. In addition, being parallel to , it is combined as a single conductance with , as (). It is to be noted that the lumped source resistance (a small value in the range of few ohms) in the -model is actually a distributed source diffusion resistance which is (based on the definition of and ) physically interlaced (inter-located) with the source-end location of and as indicated by the diagram in Figure 2(g). Hence for ease in analysis, () can be moved to the other terminal of the lumped without altering the behavior of the circuit significantly as shown in the Figure 2(c). The effect of () on the overall performance of the oscillator is still included through its effect on the tank circuit at the output. However, it is well known that for the source follower configuration ( ) does not dominate the impedance looking into the source of the buffer cell and hence in any case would not have significant effect on the frequency of oscillation. The model in Figure 2(c) can be modified as shown in Figure 2(d), where a current source first enters the gate node from the grounded drain, and then leaves the gate node and enters the source node [14]. The algebraic sum of the respective currents at the nodes and are still the same as in Figure 2(c), and hence, Figure 2(d) is equivalent to Figure 2(c). Now since the current source is controlled by the voltage across it, can be replaced with the resistance as shown in Figure 2(e). Finally, the Thevenin’s equivalent admittance () between the source and the ground looking into the source (with the parallel combination of all the passive components between the source terminal and the ground disconnected being absorbable as components in the LC tank) is shown in Figure 2(f). is investigated for transition frequencies () and negative resistance of the source-follower buffer to work as a negative resistance cell. The parasitic capacitances and can form resonators with the gate inductor . Limiting values of can thus be possibly found in terms of , , and for operation as a MMW LC oscillator. From Figure 2(f) if and are initially neglected, the Thevenin’s equivalent input admittance is given by Rationalizing by multiplying both the numerator and the denominator by , The two roots of the numerator indicates that the parallel resistance looking into the source, changes sign at and which are the two approximate transition frequencies of the buffer cell and operation of buffer cell as negative resistance is possible in the region bounded by these two frequencies and constitute the limit for the frequency of oscillation of the buffer cell. Smaller values of and parasitic capacitance can lead to possible higher frequencies at which the negative resistance behavior may be sustainable.

Figure 1: Proposed CMOS source follower buffer for negative resistance and MMW LC VCO application.
Figure 2: A small signal lumped RF model of the proposed negative resistance source follower buffer cell, (b)–(e) its subsequent transformations (neglecting the small resistances and ) leading to the final lumped model in (f) to find and (g) NMOS cross-section showing the interlaced location of the distributed source resistance with respect to and .

Next for more comprehensive analysis, the transition frequencies and the negative resistance behavior is explored using MATLAB with the inclusion of the effects of and ( is found to be noncritical in this regard [12] specially being a common-drain configuration). In this case in the Laplace domain is a ratio of long polynomials, and, is given by where denotes , denotes , denotes , and denotes Making the substitution, , and collecting the real and imaginary terms, the denominator is given by Also, replacing , and collecting the real and imaginary terms, the numerator is given by, Next, rationalizing by multiplying both numerator and denominator by (complex conjugate of ), where is then computed for various circuit parameters by executing several MATLAB m-file programs. In these simulations, nominal values of  fF,   fF,   nH,   fF,    S, ,  and    for a 130 nm IBM CMOS process technology were initially set and one of the component values were varied to explore the changes in the transition frequencies and the negative resistance () behavior. Figure 3 shows the variation of due to varying between 0.01 S and 0.022 S. There are two in this case almost anchored at 80 GHz and 220 GHz irrespective of the variation of , and a maxima (its smallest magnitude) is achieved at around 130 GHz which is also largely invariant with only increasing slightly with lower values of . Figure 4 shows that, different values of the parasitic gate capacitance lead to a different set of transition frequencies with the range and interval of the becoming higher with lower values of . In addition, the negative resistance maxima is achieved at lower values of . MMW LC VCO operation in the 150 GHz to 225 GHz may be possible with a   fF. Figure 5 shows the variation of with . With too low a value of the negative resistance behavior ceases, but using reasonably low    nH operation near 300 GHz may be possible. Larger values of leads to lower frequencies and lower values of the maxima. Also, the for close values overlap to some extent as can be observed in Figures 5, 6, and 7 shows the effect of reducing and respectively, on , which mostly consist of a higher value of the upper and more so in case of a reducing . The range of the negative resistance behavior also becomes wider with the possibility of operating close to 350 GHz. The frequencies and the possible range of negative resistance maxima values are thus found to be limited only by technology scaling [15] and the parasitic capacitances of the MOS device.

Figure 3: Variation of with .
Figure 4: Variation of with gate-to-ground parasitic capacitance .
Figure 5: Variation of with gate-to-ground inductance .
Figure 6: Variation of with gate resistance .
Figure 7: Variation of with source resistance .

3. Phase Noise Considerations in the Negative Resistance Buffer Cell

Figure 8 shows a practical noise inserted circuit diagram for the negative resistance source-follower buffer cell. The main device noise sources are the thermal gate current noise, the thermal drain current noise, and the flicker noise ( noise). The drain current noise power spectral density [16] of the MOSFET is given by  A2/Hz, while the gate current noise power spectral density is given by,  A2/Hz. In these noise expressions,is the Boltzman constant, is the temperature in absolute scale, and are, respectively, the coefficients of the channel thermal noise and the gate thermal noise which depends on the channel length of the MOSFET device. Also,, with being the zero-bias drain-to-source (channel) conductance (@ zero ) of the MOSFET device [16]. The gate current noise in the MOSFET is due to the gate-oxide capacitive coupling of the random channel charge fluctuations at radio frequencies, which is thus cross-correlated with the drain current noise. This cross-correlation is given by a factor, for the MOSFET , with,. For long-channel MOSFETs , and   0.395. Short channel effects changes these factors considerably. Using , the correlated and the uncorrelated parts of the gate current noise are, and , respectively, for the MOSFET . The flicker noise (noise ) is given by,  A2/Hz [17, 18], where the flicker noise coefficient F-A, is the device channel length, is the bias drain current and is the oxide capacitance per unit channel area. The total mean squared output noise current power parallel to the tank at the source of is then given by Or after expanding the cross-correlation, Or This composite device noise current manifests as a phase noise “skirt” [19] of the output frequency of oscillation across the tank circuit at the source terminal of the buffer cell. Figure 9 shows a typical plot of oscillator phase noise in terms of the normalized single-sideband noise spectral density ( in dBc/Hz at a frequency offset of ) which consists of three separate regions, a region at very small offsets, a region, and a constant noise floor extending into higher frequency offsets from the oscillator center frequency [20]. All the white noise components (such as thermal drain current noise and induced gate noise) fold into phase noise near the oscillator center frequency in the region, while, the low frequency flicker noise (i.e., MOS noise) is upconverted into close-in phase noise in the region. Any noise current source with noise current power spectral density (PSD),, at the buffer cell output, containing noise will have aregion in the phase noise spectrum. The flat noise floor would arise from the white noise floor of output pad devices which is not filtered by the LC tank of the buffer cell. As can be seen from (10) there is a tradeoff between bias current and device dimension for minimizing the phase noise of a VCO (voltage controlled oscillator) implementation using the buffer cell.

Figure 8: A practical noise inserted CMOS negative resistance buffer cell with component values, bias circuit, and varactor tuned tank.
Figure 9: Typical phase noise plot of output oscillation versus offset from the center frequency of the negative resistance buffer cell.

4. Spice Simulation Results

In order to verify the theoretical derivations of and negative resistance of the inductively terminated CMOS source-follower buffer cell, SPICE simulations (using Tanner Tools Pro T-SPICE V.12 and Synopsys HSPICE-RF) were conducted. The IBM 0.13 μm 8M1P CMOS process with level 49 typical device parameters were used for this purpose. These level 49 SPICE parameters accounted for the RF performance constraints due to all the parasitic junctions, overlap and fringe capacitances associated with the gate, drain, source, and body of the MOSFET device. The circuit in Figure 8 was used for the simulations. The required gate bias voltage can be set using an appropriate current mirror as shown. is a large shunt capacitor in order to AC ground the V bias connection to the inductively terminated gate of . Also, an PMOS varactor implementation [21, 22] of the tank capacitor for tuning purpose (as an MMW VCO) is also depicted in the Figure. The varactor is tuned by applying a variable positive DC voltage at the V varactor terminal with the gate terminal connected to DC ground as shown in the circuit. The unity gain frequency () of the NMOS device in the oscillator circuit of Figure 8 was above 150 GHz, and hence, oscillations at high GHz range was achievable using this device. Additional resistances for , , and were augmented to consider deteriorations of high-frequency behavior due to parasitic terminal resistances. has a slightly higher value than considering that the drain area near the channel is sometimes lightly doped (lightly doped drain, LDD) to prevent short channel hot carrier effect and hence may have a slightly higher resistance compared to the source area. In addition, the drain-to-body region near the channel of a saturated MOSFET is often depleted of carriers and hence will have somewhat higher resistance than the source-to-body region near the channel. A low- tank was used with a resonant frequency of 100 GHz. The overall frequency of oscillation is determined by the overall reactance due to the tank and the reactive component of the negative resistance cell. In order to simulate the negative resistance behavior of the buffer cell the circuit in Figure 8 was simulated by removing the tank circuit and applying an AC signal at the source node. The inductor was replaced with a large DC feed choke whose RF impedance is large compared to the impedance looking into the source node and almost all of the AC current flows into the source node. A negative resistance (as shown in Figure 10) in the range of around hundred ohms was observed which is roughly close to the values obtained through MATLAB simulations. Also, the transition frequencies were approximately close to the analytical values limited mostly by the device parasitics. Figure 11 shows the transient output of the CMOS negative resistance buffer-cell oscillator of Figure 8 indicating an output power of −19 dBm (25 mVpk) which is lower than the −5 dBm (126 mVpk) reported for the single-ended output of the VCO in [7]. On the other hand, the simulation indicates a time-period of only around 14 picoseconds for the buffer cell VCO, and Figure 12 shows the frequency spectrum (H-SPICE generated 131072-point FFT using Kaiser window) for the buffer cell oscillator output, indicating a fundamental frequency of around 70 GHz. In order to compare the proposed negative resistance buffer cell with the VCO cell of [7], a single-ended version of the VCO cell in [7] was simulated using the same 130 nm IBM CMOS process technology. The same output LC tank as the proposed buffer cell was attached to the drain terminal of this VCO cell in [7] for the simulations. In this case a wider device with higher drain current than the proposed buffer cell was required to sustain oscillations for the same drain resistance, and, an oscillation frequency of only 50 GHz. was achieved. This comparative performance of the design in [7] with respect to the proposed VCO design would not be altered significantly if were not higher than (or, if the values of and were swapped) in any possible variations in design, layout, fabrication or device operation. The time-constant due to any output buffer/pad parasitic capacitance will always be higher at the drain node (for the design in [7]) compared to that at the source node (for the proposed design) due to the smaller resistance looking into the source node compared to that looking into the drain node. The impedance looking into the source node of Mb is the sum of and , whereas, the impedance looking into the drain node is the sum of and the source degenerated impedance looking into the drain, which is much larger than the sum of the resistances at the source. Consequently, the pole at the drain node would be closer to the origin in the -plane compared to the pole at the source node. For this reason, the proposed buffer cell is inherently capable of operating at higher oscillation frequencies compared to the design in [7]. The simulated tuning range using the varactor for the buffer cell is in the range of 66 GHz to 79 GHz which is higher than the tuning range of the single-ended VCO (fundamental port) of the design in [7]. The push-push differential form of the design in [7] had an optional 114 GHz output which is obtained by canceling the fundamental and summing the second harmonics from the two single-ended outputs. This requires significant 2nd harmonic currents and proper phasing of current waveforms. Similar differential form for the buffer cell can also be created with≥140 GHz optional VCO output. In addition, this buffer cell consumed under 3 mW compared to the reported 3.6 mW (excluding the additional 4.8 mW dissipation in the output buffer) by the design in [7]. In accordance with the simulations carried out for both the circuits, with the required wider device size for sustained oscillations in case of the VCO in [7], the proposed buffer cell is expected to be more energy efficient than the VCO in [7] for certain application scenarios. The source inductor can be implemented (absorbed) by the wirebond inductance and an output buffer may be needed to drive the bonding pad and package parasitics. Also, a Total Harmonic Distortion (THD) of at least −50 dB is achieved by the proposed buffer cell oscillator as indicated by the frequency spectrum in Figure 12. This proposed negative resistance cell will thus find wide applications in 60-GHz WLAN and automotive radar systems compared to previously published MMW VCO circuits in [57].

Figure 10: SPICE simulation of the negative resistance behavior of the buffer cell.
Figure 11: Transient output of the CMOS negative resistance buffer-cell oscillator of Figure 8 indicating a time period of around 14 picoseconds.
Figure 12: Frequency spectrum for the buffer cell oscillator output indicating a fundamental frequency of around 70 GHz.
4.1. Monte Carlo Simulations for Manufacturability

In order to verify the design for manufacturability (practical implementation) extensive Monte Carlo simulations were also carried out using a Gaussian distribution function and up to 50% variation in process and geometrical parameters, supply voltage, and ambient temperature. The degradation of tank due to substrate leakage is one of the major high-frequency effects in the high GHz range in silicon integrated circuits. A bar chart is shown in Figure 13 comparing the results of all the temporal Monte Carlo simulations including the temperature variation. As can be seen from the comparison of the different bar plots, the common-drain configuration results in very small effect of the drain resistance variation, while, as expected, fluctuation of inductance (due to process and geometry variations) has the largest effect on the oscillation frequency. Gate resistance can be reduced by layout techniques discussed in [11] thereby considerably reducing its detrimental effect on . The sensitivity of the oscillator frequency with threshold voltage variation is due to the variation of the overdrive voltage resulting in a variation of the charging (pull-up)/discharging (pulld-own) current at the source node. The variation of the oscillator output power with the various parameters is also shown in the Figure 13 indicating a trend similar to that of the amplitude variation. It can thus be concluded from these thorough Monte Carlo simulations that the presented LC VCO design using the source-follower negative resistance cell is quite robust and it achieves an oscillation frequency of 70 GHz under worst possible process degradations. The results being reported here are thus expected to be roughly close to measured results from a monolithic fabrication of the proposed buffer-cell using the 130 nm CMOS process. In order to estimate the phase noise of the buffer-cell oscillator, input referred noise current power source across the LC tank (as discussed in Section 3) is assumed. The rough estimate of the phase noise was determined, using (a) the standard T-SPICE noise models (  for drain current noise) and the noise simulation setup and (b) considering the effect of noise folding due to nonlinearity related intermodulation products [19, 23] of the form , with, , being the oscillator second harmonic and being the noise tones in the vicinity of . An approximate Monte Carlo simulation (2000 simulation iterations with Process, Voltage and Temperature variations) of the phase noise spectrum for the proposed buffer cell (centered @ 77 GHz) is shown in Figure 14, indicating noise-shaping by the bandpass behavior of the output LC-tank centered at around 77 GHz (in close agreement with the FFT spectrum of Figure 12). The spectral density is given in 10−18Sq. Volts/Hz. With carrier signal level at around 17.68 mV RMS and approximate worst case phase noise at an offset of 600 KHz 2*10−18 Sq. Volts/Hz, the approximate phase noise with respect to the carrier (@ 77 GHz) is around –142 dBc/Hz at an offset of 600 KHz from the carrier. Considering all possible noise sources (e.g., injected circuit noise and other sources of thermal and noise, etc.) in a monolithic RF system, the actual measure of the phase noise is expected to be worse (higher) (>−125 dBc/Hz ). Allowable channel spacings are often constrained by achievable carrier phase noise performance at a close-in offset frequency [24], and narrow channel spacing in the hundreds of KHz is a reasonable consideration in evaluating the phase noise performance of an oscillator at such an offset from the oscillator’s center frequency. Figure 15 shows the result of similar phase noise simulation for the single-ended version of the VCO cell of [7]. The center frequency in this case (using the same LC tank) was around 50 GHz thus indicating lower achieved single-ended oscillation frequency by the VCO design in [7] compared to the proposed negative resistance buffer cell under similar simulation conditions. Also, as can be seen from the simulation, the phase noise skirt surrounding the center frequency is more irregular with wide variations with variations in process and environmental parameters compared to that for the proposed buffer cell VCO. The estimated simulated phase noise in this case is around −137 dBc/Hz (600 KHz offset from the carrier) which is higher compared to the proposed buffer cell VCO. As mentioned, it is understood that in a practical monolithic implementation the phase noise is expected to be much higher, but based on the Monte Carlo simulations, the proposed buffer cell VCO is expected to have an overall better phase noise performance compared to the design in [7].

Figure 13: Bar chart of overall temporal Monte Carlo simulations for manufacturability for 50% variation in the process, circuit, and environmental parameters.
Figure 14: Monte Carlo simulation of phase noise “skirt” near a center frequency of 77 GHz for the proposed buffer cell oscillator.
Figure 15: Monte Carlo simulation of phase noise “skirt” near a center frequency of 50 GHz for the VCO cell in [7].
4.2. Packaging and Bond-Wire Considerations

Figure 16 shows the composite lumped model of a typical packaged RF signal output interconnect path consisting of package lead frame (pin), bond-wire, and bond-pad [25]. In this model, and are, respectively, the lead-frame pin and bond-wire inductances whose values depend on the frequency and the type of packaging, and are, respectively, the lead-frame pin and bond-pad capacitances whose values mostly depend on the type of package. Also, (substrate resistance) accounts for the finite -factor of the package. Packaging issues were not discussed in [7] and the output buffer was used to drive an on-wafer 50 Ω probe on the probe pad. Such buffers are easily designed using a source follower to match its output impedance () to 50 Ω transmission line characteristic impedance. For packaging consideration at such high RF/MW frequencies, the flip-chip or control-collapse-chip-connection (C4) option utilizing solder bumps may be desirable for direct connection of RF output to 50 Ω PCB transmission line. For other possible packaging options (such as Ball Grid Array) off-chip microstrip line matching to 50 Ω may be necessary. In such a case, in order to minimize ground path inductance [25], several pins (wire bonded to separate die grounds) should be connected to the PCB ground plane and also downbonded to the package (carrier) substrate (package ground plane). In order to use bond wire for the source inductor , several parallel bond wires may be needed along with down-bonding to package substrate (package ground plane) in order to bring down the source inductance to the desired value (0.8 nH in this case) from a value of 1 to 2 nH for each bond wire.

Figure 16: Lumped-element model of package pin, wirebond, and bondpad.

5. Conclusion

An MMW LC VCO exploring the transition frequencies () and the negative resistance of an inductively terminated source follower buffer cell has been proposed. The frequencies and possible range of negative resistance maxima values has been found to be limited only by technology scaling and the parasitic capacitances of the MOS device. A of over 250 GHz can be obtained for a circuit using 130 nm CMOS process technology, and simulated oscillations at 70 GHz (limited only by the tank’s reactance) was demonstrated using a low- LC tank at the source output. Extensive Monte Carlo simulations prove that the presented design is quite robust to process degradations and high GHz substrate leakage in a practical implementation as well as to significant power supply scaling. A noise analysis was also carried out.


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