Abstract
The design of a narrow-band cascode CMOS inductive source-degenerated low noise amplifier (LNA) for 866 MHz UHF RFID reader is presented. Compared to other previously reported narrow-band LNA designs, in this paper the finite effect has been considered to improve the nanometric design, achieving simultaneous impedance and minimum noise matching at a very low power drain of 850 from a 0.7 V supply voltage. The LNA was fabricated using the IBM 130 nm CMOS process delivering a forward power gain () of , a reverse isolation () of , an output power reflection ( @866 MHz) of , and an input power reflection ( @866 MHz) of . It had a minimum pass-band of around 2.2 dB and a third-order input referred intercept point (IIP3) of .
1. Introduction
RFID (radio-frequency identification) is one of the fastest growing wireless communication technologies for commercial product tracking. As the low noise amplifier (LNA) is the first block in the front-end of the RFID reader which is tuned at a certain transreceiver frequency, it needs to be designed optimally to minimize the noise for the following stages and avoid the distortion of the source signal (requires good linearity). To overcome design trade-off difficulties between gain, power, noise figure and matching in the optimization of the LNA, the design of the matching circuits at the input and the output are based, respectively, on minimal and maximal power transfer. In recent years, considerable research on CMOS LNA design in submicron technologies at 900 MHz have been reported by many authors in [1–4]. A lower frequency standard for UHF RFID at 866 MHz is also implemented in Europe, Africa, and New Zealand. Low power dissipation at low supply voltage is a significant design criterion for RFID applications synthesized by design trade-off between gain, , input and output impedance matching and high linearity. In this paper we discuss the design and the experimental results for a 0.7 V low-power 130 nm CMOS 866 MHz single-ended common-source telescopic cascode LNA using an power constrained simultaneous noise and impedance matching (PCSNIM [5, 6]) technique.
2. Principles and Circuit Design
An inductively source degenerated telescopic cascode topology has been chosen for the 866 MHz RFID LNA design due to its current reuse structure and hence it consumes less bias current than the folded cascode. Figure 1 shows the circuit diagram of the proposed RFID LNA. and forms the cascode configuration and their bias currents are driven by and . , and form the output tank circuit tuned at 866 MHz with an angular frequency bandwidth of . denotes ac-coupling capacitor (one at the source input and the other at the output load) while is an ac grounding capacitor at the gate of the cascoding device . provides the inductive source degeneration. An improved PCSNIM technique is adopted here for the telescopic cascode LNA structure optimization. is in parallel with of in order to achieve minimum noise figure with power constraint and higher unity gain frequency . Optimal impedance for noise match can be derived to achieve the theoretical [5, 6]. The effect of the finite device conductance due to the deeply scaled short channel length is included in this design optimization. With regard to the input impedance matching at resonance, we can easily derive where equals , () is the output conductance of , while and are the transconductances of the cascode transistors and , respectively. Typically at resonance changed by 6%–12% due to the inclusion of in (1) as indicated by the plot in Figure 2 of the analytical with variation in the of (being around 450 ohms in this design) from the long channel assumption . In addition, as shown in Figure 2, the extent of inaccuracy with long channel assumption also varies with the chosen value of , the source inductor. Equation (1) also indicates that for deep nanometric design the finite output conductance of adds an additional trade-off factor in determining the value of the capacitor (in ) required for achieving power-constrained input matching. Changing the overdrive and/or the geometry of (and hence ) in relation to provides an additional degree of freedom to reach this value of for input matching. Essentially this trade-off enables a lower value of and hence a higher in achieving input impedance matching for a given . In addition, inclusion of the finite effect provides a more accurate power constrained simultaneous optimization of noise and impedance matching for nanometric CMOS (hence it is termed enhanced PCSNIM). The -domain gain transfer function of the RFID LNA can be determined by first finding the short circuit transconductance () and then the open circuit output impedance () at the drain of . Hence, we can deduce the voltage gain aswhere is the source resistance, is the series resistance of the gate inductor, RLs is the series resistance of the source inductor, and is an equivalent gate resistance due to the addition of , which is smaller than the original gate resistance of the transistor . The dB magnitude comparison of the theoretical (analytical) gain with the simulated gain is shown in Figure 3 indicating close agreement between the two. A technique based on determining the short circuit output noise current power at the drain of was used for the noise analysis. In this method the output load is shorted compared to the method in [5] where the output noise current is determined with the output load. Since the noise factor is defined as the ratio of the total mean-squared output noise current due to all the noise sources to the input source only, and as the noise factor mostly depends on the front-end noise sources farthest from the output load, almost the same value of noise factor is obtained using this technique without the extra calculation, compared to if the output noise current with load is used in the computation. Hence, the noise factors of the front-end noise sources using this short circuit output noise current method, are added to obtain the overall frequency behavior of the noise factor given bywhere denotes . It is evident from (3) that inclusion of () provides a more detailed expression and hence a more accurate estimate of the noise factor.
3. Simulation and Experimental Results
The LNA (as part T8BTAU) was fabricated using the 130 nm IBM CMOS process available through MOSIS. Figure 4 shows the microphotograph of the 0.571 sq.mm die. The outer diameters of the inductors were, respectively, 240 for and 140 for with 5 wide trace of top thick aluminum layer MA and underpass contact copper layer E1. The capacitors and were fabricated as MIM (metal-insulator-metal) capacitors, and the resistors were fabricated using p+ poly layer with high-sheet resistance (340 /□). Figure 5 shows the simulated and measured forward power gain, under matched condition [8], indicating reasonably high-Q tuning at 866 MHz with measurement being 4 dB below simulation due to loss along external matching circuit. The measured input reflection coefficient is approximately ≈−12 dB at 866 MHz as shown in Figure 6, while the output reflection coefficient is measured to be ≈−25 dB at 866 MHz as shown in Figure 7. These measurements were carried out using external matching elements and indicates close agreement with the simulation. All measurements include trace and connector losses. Figure 8 shows the comparison of the analytical, simulated and measured spectrum which verifies the close approximation provided by (3) due to the inclusion of the finite effect. The measured NF was around 2.2 dB. The IIP3 and the 1-dB compression points were determined to be −11.5 dBm and −16.1 dBm, respectively, as shown in Figure 9. Finally, Table 1 shows a summary of performance comparison of the proposed UHF LNA with other UHF LNA designs indicating the low NF achieved at sub-mW power.
4. Conclusion
The improved power constrained optimization of an UHF RFID LNA design at 866 MHz considering finite effects is presented and measurement results are demonstrated. The design achieves very low using only a 0.7 V supply voltage and consuming only 850