Active and Passive Electronic Components

Volume 2012, Article ID 276145, 7 pages

http://dx.doi.org/10.1155/2012/276145

## Modeling of Current-Voltage Characteristics of the Photoactivated Device Based on SOI Technology

Faculty of Engineering, Bar Ilan University, 52900 Ramat Gan, Israel

Received 31 July 2011; Revised 14 November 2011; Accepted 1 December 2011

Academic Editor: Abdelkarim Mercha

Copyright © 2012 Doron Abraham et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

An analytical model of the silicon on insulator photoactivated modulator (SOI-PAM) device is presented in order to describe the concept of this novel device in which the information is electronic while the modulation command is optical. The model, relying on the classic Shockley’s analysis, is simple and useful for analyzing and synthesizing the voltage-current relations of the device at low drain voltage. Analytical expressions were derived for the output current as function of the input drain and gate voltages with a parameterization of the physical values such as the doping concentrations, channel and oxide thicknesses, and the optical control energy. A prototype SOI-PAM device having an area of 4 *μ*m × 3 *μ*m with known parameters is used to experimentally validate and support the model. Finally, the model allows the understanding of the physical mechanisms inside the device for both dark and under illumination conditions, and it will be used to optimize and to find the performance limits of the device.

#### 1. Introduction

Silicon-based nanophotonic devices have attracted appreciable attention and effort because of their potential applications in silicon-integrated circuits. Although silicon may be not the ideal platform for optical devices, the usage of silicon is mandatory for the generation of optoelectronic integrated circuitry. The quality of commercial silicon on insulator (SOI) wafers driven by the microelectronics industry still continues to improve while the cost continues to decrease. Moreover, as previously mentioned the compatibility with silicon integrated circuits manufacturing is an important reason for this interest in silicon photonics [1].

The optical capabilities are used to overcome some limits of the non optical devices. Those capabilities are high propagation velocity, reduced cross talks and absence of noise coupled by electrical inductance and capacitance [2–4]. Such devices can operate at very low operational power and have parallel processing capabilities [5, 6].

In this paper, we present the first analytic model of the previously presented hybrid optical-electrical device, the *silicon on insulator photo-activated modulator* (SOI-PAM) [7]. As deduced from its name, the device is controlled by optical command. like a junction field effect transistor (JFET), the information current flows between two terminals (source and drain) in a silicon channel. The device concept relays on the fact that the thickness of depletion layer in the channel, which affects the information current, can be controlled through external illumination and not only by applying a gate voltage.

The model was developed for the linear domain of the channel (drain to source) current voltage characteristic and adapted to experimental measurements.

In Section 2, we describe the operation principle of the SOIPAM device. In Section 3, we present the general assumptions for the model. In Section 4, we derive the analytical model in the depletion mode and in Section 5, we develop unified lineal model and extract its parameters. Section 6 concludes the paper.

#### 2. SOI-PAM Device

The device is based on a structure consisting of a thin n-type silicon layer (30 nm) on insulator above p-type substrate (SOI-bonded wafer) [8]. The n-type layer was obtained by compensation of the original low-doped p-type silicon layer using an ion implantation of phosphorus.

As depicted in Figure 1, the channel is delimited by source and drain ohmic contacts made of doped polysilicon. The length of the channel is about few microns as fabricated in the prototype version of the device [8]. The information channel is insulated from the p-type substrate by a buried oxide layer having a thickness of 150 nm (SOI wafer). The device is insulated from the surrounding devices by a thicker thermal field oxide.

In principle, when a given negative gate potential is applied to the bottom side of the p-type substrate, a negatively charged depletion layer appears under the buried oxide layer. As a result, a positively charged depletion layer appears inside the n-type channel. Since the n-type doping level (donors concentration of of about 10^{17} cm^{−3}) of the channel is designed to be larger than the p-type substrate (acceptors concentration of 10^{15} cm^{−3}), the thickness of the depletion layer in the n-type area is narrower than the depletion layer in the p-type region. Moreover, the device is designed in such a way that, in dark conditions, the depletion layer in the channel is smaller than the channel thickness so the device is partially depleted and can be considered as normally on, that is, moderately conducting under dark condition and zero gate voltage. Note that the gate voltage should be applied with a sufficiently high frequency (few kHz) or swept at a sufficient rate in order to bring the substrate into the “deep” depletion mode and consequently to avoid the inversion of the channel.

If a short pulse of a visible laser illuminates the area under the oxide layer (oblique illumination), the photo generated electrons will accumulate at the bottom silicon-oxide interface and consequently increase the positively charged depletion layer in the channel. With a pulse of sufficient energy, the channel will be cut off. In a future version of the device, a sweeping potential will be added so that the modulation will be limited by the drift time of the photogenerated carriers in a micrometric region rather than by the time consuming recombination process. Assuming a saturation velocity of 10^{7} cm/s and a one micron sweeping length, the drift time is expected to be as small as 10 ps, that is, achievable modulation rates can be as high as 100 GHz.

#### 3. General Assumptions

In a similar way used for other field effect devices, the 2D-Poisson’s equation will be solved in one dimension (which is the axis that is being perpendicular to the plane of the Si-SiO_{2}-Si interface) by assuming the Shockley’s Gradual Channel Approximation (GCA) [9]. For small drain voltage values, it is reasonable to assume that the electric field varies more rapidly in the direction than the variations of the lateral field along the channel direction ( axis) due to the large ratio between the channel length and the buried oxide thickness.

The geometry of the device is sketched in Figure 1. The channel, having a length of 3 *μ*m, is assumed to be along the direction. The thickness of the channel is 30 nm and is measured in the direction. The width of the device is 4 *μ*m measured in the direction. The channel potential is a function of the distance along the channel.

In order to derive an expression for the drain current, it is useful to make some simplifying assumptions.(1)All the regions of the device are assumed to be uniformly doped.(2)The current flow occurs only within the nondepleted (neutral) portion of the channel.(3)The mobility of the carriers is not drain voltage dependent (low field mobility is mainly gate voltage dependent).(4)The oxide is an ideal insulator such the oxide and interface charges are negligible.(5)The contact series resistances are negligible.(6)The generation current is negligible.

#### 4. Derivation of the Analytic Model for the Depletion Mode

The Poisson’s equation is solved separately for each region of the SOI-PAM device structure composed by a p-n depleted junction separated by an oxide layer. As supposed in the GCA approximation, the channel voltage induced by the drain-source bias is added to the applied negative gate voltage according to the following equation: where , are the potentials in n-type depleted region, p-type depleted region and the oxide layer respectively. is the Flat Band (FB) bias of the SOI-PAM device that includes the built-in bias of the p-n junction and the work function differences between the contact metals and the silicon regions (substrate and channel, resp.). Oxide and interface charges are considered to be negligible. Finally, we get from (1) that: where and are the depletion thicknesses of the n and p-type areas respectively. are the dielectric permittivities of silicon oxide and silicon, respectively. Then, the charge neutrality of the device is expressed in the following equation:

The channel depletion layer thickness, , can be solved accordingly: where is defined as the oxide coupling factor (dimensionless): and is the oxide coupling voltage defined as:

We can easily check that the depleted is zero for equals , that is, the flat band voltage is the transition between accumulation and depletion modes as for MOS capacitor.

The maximum value of equals to when the corresponding gate voltage , equals to the threshold (or cut off) voltage when taken without drain voltage . Then from (4) we obtain: where is the internal pinch off voltage for the device without oxide and at zero drain voltage as following:

Assuming that the drain current , flowing in the neutral upper part of the depleted channel, is constant along the axis, we can write that:

By integrating the expression for between 0 and we get the oxide-modified Shockley’s equation for drain current (as far as ): where is the maximum value of the conductance (for undepleted channel).

One can then derive the channel conductance of the SOI-PAM device from (10):

In the depleted case (where , that is, ) the channel conductance does not longer depend on but on . So, according to (12) and (4), the conductance can be simply related to the closure of the channel by the depletion region entirely controlled by as following:

At the saturation point, for a given , the drain current reaches its maximum value, so that the saturation voltage is obtained by zeroing the channel conductance , in (12), yielding:

From (7) the threshold voltage is expected to be high in the device, so the saturation will not occurred for the relatively small values of considered in the depletion mode.

According the above equations, we can derive some qualitative expectations on the influence of material parameters on the conductance . According to (11) and (12) is increased by increasing: the channel doping concentration or the channel thickness or also the buried oxide thickness . Also, gd is increased by decreasing the substrate concentration . Finally, we can notice that for the limit case where the oxide layer vanishes () both the silicon oxide coupling factor in (5) and the silicon oxide coupling voltage in (6) vanish while equals to the junction’s built-in voltage . So, the above expressions (12)–(14) are reduced to those describing a classic JFET n-channel device (for which ).

#### 5. The Unified Linear Model and Parameters Extraction

##### 5.1. - Characteristics and Operation Modes

A prototype of the constructed SOI-PAM device was experimentally characterized using the Keithley SCS-4200 parameter analyzer. As seen in Figure 2, the - characteristics are measured over [−4 V, 4 V] range for several low values (0.1–0.5 V) in order to get a linear relation between and .

In this section we develop a unified model of the - characteristics based on the MESFET unified model [9] available for the three operation modes of the device and at low values. A similar approach was used by Colinge for a SOI p-channel MOSFET [10].

*(1) Accumulation Mode ()*

The n-channel is conducting through the accumulation layer of majority carriers located at the top of the silicon-buried oxide interface. The electron concentration is determined by -.

*(2) Depletion Mode ()*

The n-channel is partially depleted but is still conducting through the squeezed neutral region of the channel above the depletion region.

*(3) Diffusion Mode ()*

The n-channel is fully depleted; there is a small diffusion current flowing from the *n*^{+} source region through the *n* depleted channel. The current is controlled exponentially by the gate voltage as observed in MESFET devices [9]. The sweep is performed quickly enough such the channel inversion is not achieved so the channel is considered in a “deep depletion” state.

We will now express the drain current model for each one of those mode as following:

*(1) Accumulation Mode ()*

The linear drain current can be described by the following relation as observed in the pseudo-MOSFET device [11]:
where is the buried oxide capacitance per unit area, given by:

From the linear extrapolation at positive values of , we can extract the values of (~0.1 V) and (~700 cm^{2}/Vs) which are roughly constant with . The extracted mobility value is found consistent with the similar thin pseudo SOI-MOSFET [11] having the same silicon film thickness and the doping concentration range of the n-channel (10^{17} cm^{−3}). However due to the non uniformity of the ion implant process, the doping value is not precisely known for each device. Moreover due to the rapid variation of the mobility with doping concentration in this range (10^{17} cm^{−3}), the doping concentration cannot be extracted accurately from the mobility.

*(2) Depletion Mode ()*

The drain current in the partially depleted channel can be rewritten by the following relation [9]:
with being the electron sheet density in the channel above the threshold voltage . This density is simply given by:
while is the thickness of the depleted region in the channel at low so it is mainly a square root function of as given by (4).

*(3) Diffusion Mode ()*

For positive values, the saturation condition () is always satisfied in this mode, so the drain current in the fully depleted channel is being described as a saturated diffusion current (independent of ) according to [9]:
where is the thermal voltage (25.6 mV at room temperature) and is the electron sheet density in the channel below the threshold voltage . For larger than , is defined by a Boltzmann’s distribution like:
with being the electron sheet density at [9]:

And is the fully depleted silicon channel capacitance per unit area at , given by:*η* is the ideality factor extracted from the slope of the sub-threshold exponential fit and is evaluated to be 11.5 as the mean value over several values as seen in Figure 2(b). This value is comparable to the / ratio as also reported in the subthreshold current model for MOSFET devices [9].

According to (19) and (20), the threshold voltage can be extracted as the departure point of the exponential fit [9] and is found to be −2.3 V as shown in Figure 2(b) for equals 0.1 V. The corresponding threshold current is 25 nA which is the maximum diffusion current allowed in the channel.

However, according to (7), the expected value of is −9 V. Actually, the measured current is not vanishing at −9 V. Moreover, the depletion current is a power law function of while the diffusion current is an exponential decay with below −2.3 V. So the diffusion is the limiting process in the subthreshold mode. Consequently, the measured drain current can be modeled by the following expression [9]: Experimentally (see Figure 2(b)), is found to be slightly dependent in spite of the saturation condition assumed above. In fact, we can link this dependence to those of with at low values. This is similar to the DIBL effect found in MOSFET’s devices [9]. The values are extracted from the threshold current fixed at 25 nA for each - from Figure 2(b). For instance, for equals 0.5 V, the extracted value is −2.6 V. These values are used in the model.

##### 5.2. Fine Tuning of the Doping Concentration

Due to the lack of accuracy of the doping concentration, this latter can be refined in order that (23) will best fit the measured dain current in Figure 2(b) in particular at V. The matching value for is found as 8 × 10^{16} cm^{−3}, instead of the initial designed value of 10^{17} cm^{−3}, but still reasonable in regard to the doping distribution. This tuning is performed according the mobility voltage-dependent model as presented below.

##### 5.3. Mobility Voltage Dependence

The electron mobility can be evaluated from the extracted threshold voltage (−2.3 V) using (19) and (20) as follows:

This mobility value is found to be much lower than the value measured in the accumulation mode (700 cm^{2}/Vs). This is not surprising since the low field mobility in the depletion mode is reported to increase rapidly for gate voltages above in MESFET devices [12]. This should be explained by the decreasing of the depletion layer while increasing above . According to this reference, we can expect a linear relation of the mobility with in order to match the experimental - characteristics in the depletion mode like

Another assumption is necessary for the physical coherence of the proposed model. On the one hand, the mobility cannot vanish with so it should be pinned to the lower threshold limit value of 200 cm^{2}/Vs even for values below . On the other hand, for the continuity sake, the depletion current above , should match the accumulation current voltage [11]. So the current matching between the accumulation and the depletion current (for which ) may occur at a specific “effective” flat band bias defined as follows:
the expression of is consequently given by
with: cm^{−3}.

This “effective” flat band bias value actually defines the lower limit of for which the accumulation current may be described by (15). Also, defines the upper limit of for which the depletion current may be described by (10).

The mobility variation with can finally be modeled by using the following step function:

The comparison between the experimental characterization and the unified model as described in this section shows a satisfying matching for values of 0.1 V and 0.5 V as can be seen from Figures 2(a) and 2(b).

##### 5.4. Characteristics

In order to confirm and complete the current-voltage model of the SOI-PAM device, the measured characteristics are presented in Figure 3. The unified model is used to simulate these characteristics up to the saturation region for equals −1, 0, 1, 2, and 3 V, respectively, and for positive values up to 3 V. The linear behavior of the drain current in the saturation region can be interpreted as a drain-induced channel length modulation [9].

For equals 3 V, the device is in the accumulation mode so the corresponding characteristic is well fitted by (15) by adding the parabolic term in up to the saturation region as used for MOSFET device:

The saturation voltage is then defined as with equals to 0.1 V.

The measured saturation voltage (Figure 3) matches the expected value (−2.9 V).

For equals 2 V, the device is still in the accumulation mode, so the previous equation is valid till the equals , that is, 1.77 V as extracted from (26). However, a small discrepancy is observed above 1 V near the saturation region. This may happen due to an enhancement of the channel length modulation effect as mentioned above [9].

For equals 1 V, the device is now in the depletion mode, so (17) can be used to fit the corresponding characteristic by taking value of 577 cm^{2}/Vs as estimated from (28). The saturation voltage measured as 2.3 V on Figure 3, is overestimated by the modeled value (3.3 V from (14)) may be due to the velocity saturation [9] that was not included in the present model.

For equals 0 V, the contribution of the diffusion current is negligible and (17) is still sufficient to fit the corresponding characteristic by taking value of 402 cm^{2}/Vs as estimated from (28) but with slight overestimation of the current value and of as noticed above.

For equals −1 V, the contribution of the diffusion current is now not negligible and (23) is used to fit the corresponding characteristic by taking value of 227 cm^{2}/Vs as estimated from (28) but again with slight overestimation of the current value and of as noticed above.

##### 5.5. Simulation of the Illumination Effect

By synchronously and directionally illuminating the p-type substrate, the free photogenerated electrons concentration can be significantly and instantly increased to build the inversion (negatively charged) layer under the silicon oxide. Consequently, the positively charged depletion layer in the n-type channel is widening and could fully deplete the channel.

We can express the n-type drop voltage dependency by the amount of electrons that are generated by the applied illumination. The number of incident photons is related to the total energy as:
where is Planck’s constant, is the speed of light and *λ* is the photon’s wavelength. The capacitances of the partially depleted silicon layer and the buried oxide are associated in series, so the total capacitance per unit area is

Then, channel’s voltage drop, that is, the “illumination induced voltage” can be expressed by
where is the quantum efficiency of silicon for the given *λ*. So, for relatively low illumination levels, the thickness of the channel depletion layer can be increased by the illumination-induced voltage according to (4)

Consequently, the depleted channel region will grow and the depletion mode current will decrease when the illumination energy is increased, as expected from the operation principle of the device. For the actual device parameters, we can evaluate from (34) that the channel will be fully closed (for small ) by taking equals 4.5 V, that is, by supplying 75,000 photons (assuming an ideal unity quantum efficiency). In terms of light power, taking for instance, a green diode laser (*λ* = 532 nm), it would be estimated to 2.8 mW per device for a 10 ps pulse. This value can be minimized by decreasing the size of the device and increasing the oxide thickness.

Experimentally, by simply exposing the device to room (fluorescent) light, we can notice a slight positive shift of the whole characteristics as shown in Figure 4. This evidence roughly the light-induced decreasing of the drain current as expected from the present model.

Of course, a more in depth measurements of this photoelectric modulation should be performed to validate the model more accurately and will be the object of further publication.

#### 6. Conclusions

In this paper, we have derived a unified analytical model of the and characteristics for whole the operation modes of the SOI-PAM device matching the linear domain.

The analysis of the depletion mode is based on the classical Shockley’s model but originally adapted to the presence of buried oxide thickness between the n-type channel and the p-type substrate.

The effect of the light on the channel current modulation could be simply expressed as a positive shift of the gate voltage, and a qualitative behavior of the modulation has been demonstrated.

#### References

- A. Rudnitsky, A. Shahmoon, M. Nathan et al., “All-optical integrated micro logic gate,”
*Microelectronics Journal*, vol. 42, no. 2, pp. 472–476, 2011. View at Publisher · View at Google Scholar - G. Steinmeyer, “A review of ultrafast optics and optoelectronics,”
*Journal of Optics A*, vol. 5, no. 1, pp. R1–R15, 2003. View at Publisher · View at Google Scholar · View at Scopus - A. Rostami, “Low threshold and tunable all-optical switch using two-photon absorption in array of nonlinear ring resonators coupled to MZI,”
*Microelectronics Journal*, vol. 37, no. 9, pp. 976–981, 2006. View at Publisher · View at Google Scholar · View at Scopus - H. K. Tsang, C. S. Wong, T. K. Liang et al., “Optical dispersion, two-photon absorption and self-phase modulation in silicon waveguides at 1.5
*μ*m wavelength,”*Applied Physics Letters*, vol. 80, no. 3, p. 416, 2002. View at Publisher · View at Google Scholar · View at Scopus - J. Faist, “Silicon shines on,”
*Nature*, vol. 433, no. 7027, pp. 691–692, 2005. View at Publisher · View at Google Scholar · View at PubMed · View at Scopus - Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, “Micrometre-scale silicon electro-optic modulator,”
*Nature*, vol. 435, no. 7040, pp. 325–327, 2005. View at Publisher · View at Google Scholar · View at PubMed · View at Scopus - D. Abraham, Z. Zalevsky, A. Chelly, J. Shappir, and M. Rosenbluh, “Silicon on insulator photo-activated modulator,”
*Microelectronics Journal*, vol. 39, no. 12, pp. 1429–1432, 2008. View at Publisher · View at Google Scholar · View at Scopus - D. Abraham, Z. Zalevsky, A. Chelly, and J. Shappir, “Fabrication of vertically positioned silicon on insulator photo-activated modulator,”
*Photonics and Nanostructures*, vol. 7, no. 4, pp. 190–197, 2009. View at Publisher · View at Google Scholar · View at Scopus - K. Lee, M. Shur, T. A. Fjeldly, and T. Ytterdal,
*Semiconductor Device Modeling for VLSI*, Prentice Hall Series in Electronics and VLSI, chapter 4, 1993. - J. P. Colinge, “Conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFET's,”
*IEEE Transactions on Electron Devices*, vol. 37, no. 3, pp. 718–723, 1990. View at Publisher · View at Google Scholar · View at Scopus - S. Cristoloveanu, D. Munteanu, and M. S. T. Liu, “A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction, and applications,”
*IEEE Transactions on Electron Devices*, vol. 47, no. 5, pp. 1018–1027, 2000. View at Google Scholar · View at Scopus - B. J. Moon, M. J. Helix, and S. Lee, “A new technique to determine the average low-field electron mobility in MESFET using C-V measurement,”
*IEEE Transactions on Electron Devices*, vol. 39, no. 9, pp. 1982–1986, 1992. View at Publisher · View at Google Scholar · View at Scopus