Figure 1: Transfer and transconductance curves (a) and associated gate current in absolute value (b) of the device as measured during characterizations between gate stressing events. Insets show detail at regions of interest in the same data sets. Extra gate current is seen in (b) above 𝑉 𝐺 3 . 5  V after 210-minute stress (top curve) that is not seen after longer stress time (second-to-top curve). It is not known if there was a temporary test issue or if that is indeed real.