Characterization and Modeling of DHBT in InP/GaAsSb Technology for the Design and Fabrication of a Ka Band MMIC Oscillator

Abstract

This paper presents the design of an MMIC oscillator operating at a 38 GHz frequency. This circuit was fabricated by the III–V Lab with the new InP/GaAsSb Double Heterojunction Bipolar Transistor (DHBT) submicronic technology (We=700 nm). The transistor used in the circuit has a 15 μm long two-finger emitter. This paper describes the complete nonlinear modeling of this DHBT, including the cyclostationary modeling of its low frequency (LF) noise sources. The specific interest of the methodology used to design this oscillator resides in being able to choose a nonlinear operating condition of the transistor from an analysis in amplifier mode. The oscillator simulation and measurement results are compared. A 38 GHz oscillation frequency with 8.6 dBm output power and a phase noise of −80 dBc/Hz at 100 KHz offset from carrier have been measured.

1. Introduction

The developments in modern electronics (analog, digital, or mixed), whatever their intended applications (telecommunications, spectroscopy and astrophysics, plasma analysis, medical imaging, etc.) now concern applications operating from RF frequency spectrum up to the optical frequencies. In order to develop solid-state circuits operating in the millimeter wave range, new technological processes are emerging for manufacturing semiconductors operating in these domains. To achieve the performances required by such applications, a suitable solid-state technology must be available. III–V Lab provides a new InP/GaAsSb DHBT technology [1], which contains antimony in the base of the transistors and permits submicronic emitter sizes. The structure has been optimized to get an 𝐹_max greater than 300 GHz and an 𝐹_𝑇 equal to 200 GHz. In this context, the work presented in this paper demonstrates the feasibility of designing and manufacturing a low phase noise MMIC frequency source with this new technology. To provide the oscillator designer with the most relevant devices, various multifinger transistors have been measured, a number ranging from 2 to 8 have been compared and reported in [2]. For the higher-frequency applications, 2-finger devices were found to be best suited and selected for this design. In Section 2, we present the complete characterization and nonlinear modeling of the transistor, including its thermal behavior. Section 3 deals with the cyclostationary LF noise source modeling. Section 4 is devoted to the description of the oscillator design according to the new proposed methodology including the drawing of the MMIC layout. In Section 5, all the measurements are detailed and compared with the results predicted by the simulation. The last section concludes the article.

2. Transistor Modeling

In order to design oscillators with improved characteristics, we need accurate models of the passive and active elements of these circuits. The models of passive elements of this process fabricated on coplanar waveguide technology (CPW) have been developed by the MC2 Technology Company. The DHBT 𝜋 model is based on the Gummel and Poon model [3] improved in [4]. It is presented in Figure 1 with its associated thermal circuit formed by two-pole RC cells. The intrinsic part of the convective equivalent circuit is described by four diodes and one voltage-controlled current source: 𝐷_ec and 𝐷_cc control the current source with, respectively, a direct gain 𝛽_𝑓 and a reverse gain 𝛽_𝑟, 𝐷_𝑓𝑒, and 𝐷_𝑓𝑐 model leakage currents. The base collector charge 𝑞_bc results from the sum of the junction charge with “punchthrough effect” charge, and the depletion charge. The base emitter charge 𝑞_be results from the sum of three charges: the junction charge, the depletion charge due to the collector transit time, and the Kirk effect charge. These charges depend on the 𝑉_ce and 𝑉_be voltages. The extraction of parameters describing the non linear transistor model is performed from pulsed I–V, pulsed [S]-parameters measurements. More details on this currently conventional operation are given in [5, 6]. Note that this paper is a detailed version of [7] in which we will explain all the measurement and extraction procedure for the modeling and the design methodology of the oscillator.

Figure 1 

DHBT model 𝜋-topology with a two-pole RC thermal subcircuit.

To determine the thermal circuit elements, the new method proposed here is a good trade-off between speed and accuracy. This method involves the determination of the impedance and thermal time constant from the measurement of the transistor input impedance at low frequencies. Indeed, the thermal resistance can be estimated from the input impedance 𝑍_BE by (2): 𝑍_BE=𝑉_BE𝐼_𝐵=ℎ_11ISO+𝜙⋅𝑍_TH(𝜔)⋅ℎ₂₁⋅𝑉_CE0−𝑅₂⋅𝐼_𝐶0, (1) with𝜙=𝜕𝑉_BE𝜕𝑇_𝐼𝐵=CTE, (2) where 𝑉_BE and 𝐼_𝐵 are HBT Base-Emitter voltage and base current, ℎ_11ISO is the ℎ₁₁ isothermal parameter, 𝑍_TH is the thermal impedance, 𝑉_CE0 and 𝐼_𝐶0 are the bias Collector-Emitter voltage and Collector current, 𝑅₂ is the load resistance on the collector (see Figure 2).

Figure 2 

Measurements used to determine the ℎ21 parameter.

So, according to this equation, we must determine the 𝜙, ℎ₂₁, and ℎ_11ISO parameters to deduce the thermal impedance 𝑍_TH. The 𝜙 parameter is determined using the 𝐼_𝑏 measurement as a function of 𝑉_be for a constant current 𝐼_𝑐 at different temperatures in DC mode. The methodology is detailed in [8]. The ℎ₂₁ parameter is determined using the following four quantities shown in Figure 2 where 𝑍_in is the input impedance, 𝑍_out is the output impedance, 𝑍_in0 is the input impedance when the transistor output is short circuited at LF, and 𝐺_𝑑 is the transistor voltage gain. Thus, it is possible to extract the ℎ₂₁ parameter from these four measures by using the hybrid equivalent circuit of the transistor, and with (3) [9]: ℎ₂₁=𝑍_in⋅𝐺_𝑑⋅𝑅₁𝑍_out𝑍_in0−𝑅₁, (3) where 𝑅₁ is the base resistance (see Figure 2). The ℎ_11ISO parameter is determined by measuring the transistor input impedance with 𝑅₂=𝑉_ce0/𝐼_𝑐0. In this case, the measured impedance is defined by 𝑍_BE=ℎ_11ISO. At last, the input impedance is measured with a resistor 𝑅₂ different from the previous value, but at the same bias point (Figure 3). Knowing the parameters of the equation, we can deduce the thermal impedance 𝑍_th. To implement this self-heating effect in a simulator, we include a low-pass equivalent electrical circuit with two RC parallel cells in series whose impedance fits the measured 𝑍_th. Thus, it is possible to obtain an equivalence between voltage/temperature and current/power as shown in Figure 3.

Figure 3 

Determination of thermal impedance.

To conclude this first modeling step, we compare the convective model simulation with measurements. For example, Figure 4 shows the comparison of the 𝐼_𝑐(𝑉_ce) network, the current gain 𝛽 as a function of 𝑉_ce and 𝑉_be versus 𝑉_ce for an 𝐼_𝑏 current range from 0.5 mA to 3 mA in steps of 0.5 mA at a temperature equal to 25^∘C.

(a)

(b)

(c)

Figure 4 

Comparison between model (red) and I(V) measurement (blue cross) with 𝐼𝑏 current ranging 0.5 to 3.5 mA and a 𝑉ce voltage ranging 0 to 3.5 V for a temperature equal to 25∘C.

The last modeling step is the determination of the nonlinear charges 𝑞_bc and 𝑞_be by means of the pulsed [S] parameters measurements. The final modeling verification consists in comparing the complete electrothermal nonlinear model simulation with measurement. Figure 5 shows the comparison between simulation and measurement of the [S] parameters, the maximum available gain (MAG) and ℎ₂₁ parameter versus frequency for a 𝐼_𝑏 current equal to 2 mA and 𝑉_ce voltage equal to 1, 2, and 2.5 V. Thus, we get a good agreement between the two results.

(a)

(b)

(c)

Figure 5 

Comparison between model simulation results in red and measurements (blue cross) for the MAG, 𝑆11, 𝑆12, 𝑆22, 𝑆21, and ℎ21 parameters with 𝐼𝑏=2 mA and 𝑉ce=1−2−2.5 V.

3. Modeling of Transistor Low-Frequency Noise Sources

An accurate prediction of oscillator phase noise requires a cyclostationary model of the LF noise sources of the transistor [10]. A transistor model with internal LF noise sources [11] with cyclostationary properties has been developed for a GaInP/GaAs HBT technology. This model is only based on low-frequency measurements around DC bias. The noise sources variations versus the DC collector current are taken into account to elaborate cyclostationary noise model. We propose to reuse this topology (Figure 6) for this InP/GaAsSb technology with the new extraction method presented here.

Figure 6 

LF equivalent circuit of the transistor with noise sources.

This LF model of the transistor (the nonlinear charges are not represented here) is based on the original representation of Ebers and Moll (Model T), called injection model, which is based on current-controlled current sources. He directly comes from the equations of physics and models the injection currents of the transistor. 𝛼 is the large-signal forward mode current gain of a common-base transistor. More details on its equivalence to the Gummel-Poon model are given in [12]. Moreover, the extraction of noise sources from measurement is easier with this model. The diode 𝐷_be represents the base-emitter junction, 𝐷_𝑓𝑒 represents the leakage current of the base-emitter junction. The transistor effect is modeled by the controlled current source 𝛼⋅𝐼_𝑒. The current sources 𝐼_𝑐shot and 𝐼_𝑏shot are the shot noise sources, 𝐼_𝑐 and 𝐼_nc represent the LF noise sources (1/𝑓 and GR). The thermal noise sources of access resistors are negligible. The noise source 𝐼_𝑐 is generated within the base-emitter junction and it is associated to the 𝐷_eb diode. It participates in the transistor effect through the controlled current source 𝛼⋅𝐼_𝑒. The origin of the 𝐼_nc source comes from the periphery of the base-emitter junction and can be associated with the leakage diode 𝐷_𝑓𝑒. This representation with only two LF sources results from many measurements and simulations of oscillators which have shown that this transistor model is sufficient to accurately simulate oscillator phase noise. The purpose of the modeling is to extract the sources 𝐼_𝑐 and 𝐼_nc from noise measurement. In order to do that, we suppose that the transistor low-level model with its noise sources can be represented by the conventional schema of Figure 7(a) with a Norton equivalent current source at each access of the transistor. Noise measurements consist in successively measuring these two noise sources 𝐼_ecc and 𝐼_scc. To do that, two low value resistances 𝑅_in and 𝑅_out, properly chosen (𝑅_in≪𝑍_in0 and 𝑅_out≪𝑍_out0), are successively connected to each access in order to short-circuit the corresponding source [13]. Moreover, to achieve this condition, a huge capacitance is successively connected to the transistor access (in parallel with 𝑅_in or 𝑅_out of Figure 7(b) and 7(c)) where we do not measure the noise. The voltage thus generated is then amplified by the voltage amplifier and its output is connected to the FFT spectrum analyzer in order to measure the noise voltage spectral density.

(a)

(b)

(c)

Figure 7 

Equivalent circuit of a noisy transistor with current noise sources.

The schema used to obtain the noise sources of the transistor accesses is presented in Figure 8.

Figure 8 

Equivalent schema for the extraction of short-circuit noise current spectral density at transistor accesses.

This schema is the same at each access of the transistor. The amplifier is represented by its noise voltage source 𝑒_at and by its input impedance 𝑍_at. The voltage 𝑉_𝑠 is amplified with a gain G to be measured on the FFT analyzer. The [ABCD] matrix represents all the passive elements considered in the measurement (bias tees, lines, etc.). 𝑅 can be either 𝑅_in or 𝑅_out, 𝐼_𝑅 is the thermal current noise source associated to 𝑅, 𝐼_dut can be either 𝐼_ecc or 𝐼_scc, and 𝑍_dut can be either 𝑍_in0 (with the collector short-circuited) or 𝑍_out0 (with the base short-circuited). Thus, applying Kirchoff’s laws, we obtain (4): 𝑉_𝑠=𝑁₂⋅𝐼_dut+𝑁₃⋅𝑒_at+𝑁₄⋅𝐼_𝑅𝑁₁, (4)

Now, we must determine the noise voltage spectral densities at each access: 𝑆_𝑉𝑠=𝑁₂𝑁₁²𝑆_𝐼dut+𝑁₃𝑁₁²𝑆_𝑒at+𝑁₄𝑁₁²𝑆_𝐼𝑅, (5) with 𝑁₁=𝑍_at⋅𝑅⋅𝐷+𝑍_at⋅𝑅⋅𝑍_dut⋅𝐶+𝑍_polar⋅𝑍_dut⋅𝐴+𝑅⋅𝐵+𝑍_at⋅𝑍_dut⋅𝐴+𝑍_at𝑁⋅𝐵,₂=𝑍_at⋅𝑍_dut(),𝑁⋅𝑅⋅𝐴⋅𝐷−𝐵⋅𝐶₃=𝑍_at⋅−𝑅⋅𝐷−𝑅⋅𝑍_dut⋅𝐶−𝑍_dut,𝑁⋅𝐴−𝐵₄=𝑍_at⋅𝑍_dut⋅𝑅⋅𝐴+𝑅⋅𝐵. (6)

Now, we can define the short-circuit noise current spectral density, which is expressed by the following equation: 𝑆_𝐼dut=𝑁₁𝑁₂²𝑆_𝑉𝑠−𝑁₄𝑁₂²𝑆_𝐼𝑅−𝑁₃𝑁₂²𝑆_𝑒at. (7)

From the previous equation applied to each access of the transistor, we thereby obtain the expressions of the noise current spectral densities 𝑆_𝐼ecc or 𝑆_𝐼scc. The last step of this noise modeling consists in extracting the two internal noise sources spectral densities 𝑆_𝐼𝑐 and 𝑆_𝐼nc in Figure 6 with (8): 𝑆_𝐼nc𝑅=−¹²𝑅_𝐷²⋅𝛽²⋅𝑆_𝐼scc+𝑅₁²𝑅_𝐷²⋅𝑆_𝐼ecc−𝑆_𝐼𝑏shot−𝑅_𝑒²⋅𝛽²−𝑅₃²𝑅_𝐷²⋅𝛽²⋅𝑆_𝐼𝑐shot,𝑆_𝐼𝑐𝑅=−²²⋅𝑅₁²𝑅_𝐷²⋅𝑅_be²⋅𝛽²⋅𝑆_𝐼scc−𝑅₄²⋅𝑅₁²𝑅_𝐷²⋅𝑅_be²⋅𝑆_𝐼ecc+𝑅₄²⋅𝑅_𝑒²⋅𝛽²−𝑅₂²⋅𝑅₃²𝑅_𝐷²⋅𝑅_be²⋅𝛽²⋅𝑆_𝐼𝑐shot−𝑅_𝑏²𝑅_be²⋅𝑆_𝐼𝑟bb−𝑅_𝑒²𝑅_be²⋅𝑆_𝐼𝑟be, (8) with 𝑅₁=𝛽+1𝑅_be+𝑅_𝑒+𝑅_𝑏,𝑅₂=𝛽+1⋅𝑅_be+𝛽⋅𝑅_𝑒,𝑅₃=𝛽+1⋅𝑅_be+𝑅_𝑒+𝑅_𝑏,𝑅₄=𝑅_𝑒+𝑅_𝑏,𝑅_𝐷²=𝛽+1𝑅_be+𝛽𝑅_𝑒²−𝑅_𝑒+𝑅_𝑏². (9)

In order to limit the LF noise measurement time while obtaining a relatively accurate model, we will only measure the noise sources in the normal, active region where the transistor operates in oscillation condition: the area of the transistor optimum load cycle for low-phase noise operation is defined in [14], by minimizing the LF noise sources conversion. Moreover, some noise measurements have shown that in the area where the base-collector junction is negatively biased, the noise level is independent of 𝑉_ce. Thus, the measurements will only consist in noise source measurements versus collector current, for a given 𝑉_ce close to the transistor bias point for low-phase noise oscillator operation. Following this procedure, Figure 9 shows the spectral densities of the short circuit noise current at transistor access for collector currents 𝐼_𝑐0=6.7,13.5,54,108mA.

(a)

(b)

Figure 9 

Spectral densities plot of the short-circuit noise current at transistor access for collector currents 𝐼𝑐0=6.7,13.5,54,108mA.

Then, from (8), the spectral densities 𝑆_𝐼𝑐 and 𝑆_𝐼nc are computed and plotted versus 𝐼_𝑐0 in log-log plot (Figure 10) for four frequencies 100 Hz, 1 KHz, 10 KHz, and 100 KHz, which correspond to the frequencies at which oscillators are generally qualified. Note that, from the point of view of the phase noise simulation, these frequencies are independent.

(a)

(b)

Figure 10 

Plot of 𝑆ic and 𝑆𝐼nc noise current spectral densities.

The final step of noise modeling is to determine the spectral density equation of 𝑆_𝐼𝑐 and 𝑆_𝐼nc obtained by fitting the curves of (Figure 10) with an equation of the form: 𝑆_𝐼𝑥=𝐾_𝑥⋅𝐼^𝑎𝑥_𝑐, (10) where 𝐼_𝑐 is the collector current, 𝑥 is taken for nc or 𝑐.

The values of 𝐾_𝑥 and 𝑎_𝑥 are given in Table 1.

Table 1 

𝐾_𝑥 and 𝑎_𝑥 values of the internal LF noise sources for each frequency.

In summary, we extracted the LF noise model of the HBT with internal noise sources. This model was implemented in ADS [15] and will enable us to simulate the phase noise of the oscillator while taking into account the cyclostationary property of noise sources.

4. Oscillator Design

The main objective of this design is to reduce the oscillator-phase noise while retaining a significant output power (few dbm). The desired oscillation frequency is 38 GHz and the MMIC uses the CPW technology. These two goals can be controlled by the intrinsic load cycle form of the transistor in oscillation [14]. This section describes the original design methodology used to reach these objectives by controlling the nonlinear behavior of the transistor when it operates as an oscillator circuit, by means of conventional amplifier nonlinear simulation. Its specific interest is the simulation rapidity and the easy control of the load cycle shaping. Then, by computing the load impedances at transistor input and output and the corresponding voltages, we are able in oscillation to obtain a nonlinear state as close as possible to that obtained in amplifier simulation. For this purpose, the three following steps are necessary.

4.1. Transistor Analysis in Large Signal Amplifier Mode

The schema of the transistor with its bias circuits (in CPW technology) and load impedance (synthesized with an inductor and a resistor in parallel) for nonlinear amplifier simulation is presented in Figure 11.

Figure 11 

Circuit for nonlinear amplifier simulation.

After some tuning of the bias point and load impedance, the gain, the output, and added powers versus the input power are plotted in Figure 12 and the load cycle in Figure 13.

Figure 12 

Amplifier simulation results.

Figure 13 

Simulation of amplifier load line.

Thus, we obtain the values given in Table 2 for the following bias points 𝐼_𝑏0=1.5mA,𝑉_ce0=2.2V,𝐼_𝑐0=35mA, where 𝑃_𝑒 and 𝑃_𝑠 represent the transistor input and output powers, 𝐶 the gain compression. Note that to reach a sufficient output power and compression gain (to ensure oscillation after manufacturing despite technological spread), the load cycle must be close to the area where the base-collector junction conducts. From this simulation, we compute the input and output impedances 𝑍_in and 𝑍_out and voltage gain 𝐺=𝑉_out/𝑉_in. These data will serve to design the feedback circuit in order to keep this nonlinear state in oscillation as explained in the next section.

Table 2 

Load pull simulation results.

4.2. Determination of the Feedback Circuit

This step involves the determination of the feedback loop designed with transmission line and of the output circuit (matching circuit) whose schema is given in Figure 14. In this schema, the transistor input impedance 𝑍_in is synthesized with an RC circuit.

Figure 14 

Feedback loop circuit.

The goal of the linear optimization of the line widths and lengths is to obtain the same output impedance 𝑍_out and voltage gain 𝐺=𝑉_out/𝑉_in as in the previous section and by taking into account the technology and geometric constraints. Thus, the first draft of the oscillator circuit is given in Figure 15.

Figure 15 

First oscillator circuit.

4.3. Oscillator Simulation

This section describes all the necessary simulations to ensure good performances of the oscillator (stability, phase noise, etc.). The first simulation is an open-loop simulation [22]. This simulation allows us to determine the starting oscillation frequency and to verify that no other parasitic oscillations exist. In order to open the oscillation loop, a new circuit is drawn (Figure 16): the voltage-controlled current source of the transistor fundamental effect is isolated from the other elements of the transistor model and is now controlled by an external generator 𝑉_ext. All the other circuit elements are included in the feedback two-port circuit.

Figure 16 

The open loop operation.

Then the open loop gain is defined by 𝐺_OL(𝜔)=𝑉_be(𝜔)𝑉_ext(𝜔). (11)

The conditions to obtain oscillation starting are given by (12):𝐺𝑗𝜔₀⋅𝐻𝑗𝜔₀𝐺>1,arg𝑗𝜔₀⋅𝐻𝑗𝜔₀𝐺=0,𝜕arg𝑗𝜔⋅𝐻𝑗𝜔𝜕𝜔_𝜔0<0, (12)

Figure 17(a) shows this simulated open-loop gain for the oscillator circuit of Figure 15. A parasitic oscillation appears at frequency 5.67 GHz. An RC series circuit has been added in parallel with the bias circuit to eliminate these oscillations. The new open loop gain is shown in Figure 17(b).

(a)

(b)

Figure 17 

Magnitude and phase of open loop gain.

We can note only one starting oscillation frequency at 37.08 GHz. This open-loop analysis also allows to compute the oscillator loaded quality factor with expression (13) [23]:𝑄_Loscill𝜔₀=𝜔₀2𝑑arg𝐺_ol𝑗𝜔𝑑𝜔_𝜔0. (13)

The quality factor obtained by this simulation is equal to 33. Now, we perform a Harmonic Balance simulation of the oscillator. The time domain waveform of 𝐼_𝑐 current and 𝑉_ce voltage are shown in Figure 18.

Figure 18 

Intrinsic time domain waveform of 𝐼𝑐 current and 𝑉ce voltage.

The intrinsic load line cycle is shown in Figure 19.

Figure 19 

Oscillator intrinsic load line.

Finally, the oscillator electrical performances are detailed in Table 3.

Table 3 

Simulated oscillator preformances.

The simulation of the oscillator phase noise (PN) is shown Figure 20.

Figure 20 

Phase noise simulation result.

Table 4 presents the contribution of elementary noise sources of the internal transistor at the 100 KHz frequency.

Table 4 

Contribution of elementary noise sources to total phase noise at 100 kHz from the carrier.

The final layout, taking into account all the technological constraints, including stabilizing circuits and a 3 dB attenuator at the output to reduce pulling effect, is shown Figure 21. The circuit was fabricated by III–V Lab.

Figure 21 

Oscillator layout (2070×1635𝜇m2).

5. Oscillator Measurement

5.1. Power and Oscillation Frequency Measurement

To test the robustness of the oscillation, measurements have been performed on 15 oscillators of the wafer for various DC 𝐼_𝑐 currents. Figure 22 presents the oscillation frequency and the output power versus 𝐼_𝑐0 current for different 𝑉_ce0 voltages and a 𝑉_be0 voltage equal to 0.8 V.

(a)

(b)

Figure 22 

Measurement result of oscillation frequency and output power versus 𝐼𝑐 current for 𝑉be0 voltage equal to 0.8 V.

The output power increases by 5 dB over the variation range of 𝐼_𝑐0, while the oscillation frequency shows a variation of 1 GHz over the same range. This shows that the oscillation frequency remains stable for an 𝐼_𝑐0 current variation between 35 and 60 mA.

5.2. Phase Noise Measurement

The XLIM Laboratory has an AEROFLEX PN9500 bench (Figure 23) to perform the phase noise measurement of the oscillator. This bench enables us measure the phase noise of the oscillator in the 250 MHz–26.5 GHz bandwidth with down-converter. The oscillation frequency of the circuit being out of range, we developed our own down-converter to reduce the oscillation frequency in the PN9500 bandwidth. Thus, the system using the delay line method is presented Figure 24.

Figure 23 

Synoptic of PN9500 phase noise bench.

Figure 24 

Principle of realized phase noise bench.

It is composed of a mixer in which an LO signal at frequency 10.75 GHz is generated by a high spectral purity synthesizer PN9276-20 from the PN9500 setup bench. The RF signal comes from the measured oscillator. The IF output is connected to the PN9718 input. Before measuring the oscillator phase noise, we must ensure that the measurement chain will not add noise. To do that, we replace the oscillator by a high spectral purity synthesized source (ANRITSU 68367C). The phase noise of the system measured with this source is represented in Figure 25 and gives the noise floor of the system.

Figure 25 

PN floor of the system.

Figure 26 shows the plot of the phase noise measurement of the 15 oscillators on the wafer and the simulated phase noise for the bias point 𝑉_be0 = 0.8 V and 𝑉_ce0 = 2.2 V.

Figure 26 

Comparison between measurement and simulation of oscillator phase noise.

We can note that the phase noise simulation coincides with the average results of measurement. The oscillation frequency measurement for the nominal bias point is close to 37.1 GHz with an output power equal to 5.2 Bm. The phase noise measure is much higher than the system PN floor (>15dB), so we can confirm that the phase noise is that of the oscillator. To compare our oscillator with published oscillators with an oscillation frequency close to 38 GHz, we will use a figure of merit described by (14):FOM=ℒ𝑓_of𝑓set𝑓−20log⁰𝑓_ref𝑓−25log^of𝑓setref𝑓_of𝑓set−20logTB%𝑃100−10log^out1mW (14) where ℒ{𝑓_of𝑓set} is the oscillator phase noise at a frequency offset from carrier 𝑓_of𝑓set. The oscillation frequency of the various oscillators (𝑓₀) is reduced to a reference frequency (𝑓_ref=37.1GHz) which is the oscillation frequency of the oscillator of this work. The carrier frequency offset is reduced to a distance 𝑓_of𝑓setref=100KHz. The multiplier factor is equal to 25 because the oscillator phase noise of this work has a slope of −25 dB/decade. The tuning bandwidth TB (in percentage) is also taken into account. The oscillator output power 𝑃_out is reduced to a reference of 1 mW. This figure of merit is valid for oscillator with a tuning bandwidth of more than 1%: otherwise, these oscillators are considered as fixed-frequency oscillators. The results are summarized in Table 5. We have chosen a value of phase noise of −80 dBc/Hz which corresponds to an average value of all those measured. We can verify that we obtain an average performance as regarding the figure of merit compared to those published.

Table 5 

Comparison of oscillator performances.

6. Conclusion

In conclusion, this work enables us to build an MMIC Ka-band oscillator with good performances. An electrothermal nonlinear model of the transistor was proposed, including cyclostationary noise sources to accurately predict its phase noise. The design method used allowed us to define a nonlinear operation of the transistor to limit the contributions of low-frequency noise sources responsible for the phase noise. This amplifier nonlinear state has been kept in oscillation operation. This evaluation of the III–V Lab process has given encouraging results concerning the feasibility of efficient Ka-band circuits.

Acknowledgment

The authors thank to Philippe Berdaguer for his participation to the technological process of circuits fabrication. Support from the French National Research Agency (Agence Nationale pour la Recherche) through the ANR/pNano ATTHENA program is gratefully acknowledged.