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Yi-Lin Yang, Wenqi Zhang, Chi-Yun Cheng, Wen-kuan Yeh, "The Improvement of Reliability of High-k/Metal Gate pMOSFET Device with Various PMA Conditions", Active and Passive Electronic Components, vol. 2012, Article ID 872494, 4 pages, 2012. https://doi.org/10.1155/2012/872494
The Improvement of Reliability of High-k/Metal Gate pMOSFET Device with Various PMA Conditions
The oxygen and nitrogen were shown to diffuse through the TiN layer in the high-k/metal gate devices during PMA. Both the oxygen and nitrogen annealing will reduce the gate leakage current without increasing oxide thickness. The threshold voltages of the devices changed with various PMA conditions. The reliability of the devices, especially for the oxygen annealed devices, was improved after PMA treatments.
High-k/metal gates are needed to continuous device scaling-down. However, threshold voltage instability and performance degradation are important problems for high-k devices . The defect density in the interface of gate stack is the major cause for negative bias temperature instability (NBTI) as well as mobility degradation . Oxygen vacancy is known to play an important role in threshold voltage variations  and is a significant defect in the HfO2/Si system . The influence of charge oxygen vacancies introduces a dipole offset between the gate metal and the substrate .
Post metallization annealing (PMA) is used to reduce the defects at the interface, such as fixed oxide charges, oxide trapped charges, and interface charges . Previous work has demonstrated that oxygen vacancies can be passivated for device with noble metal gate by oxygen diffusion through the gate metal . However, these suffer from high equivalent oxide thickness. In this work, we show that both oxygen and nitrogen can be diffused through thin TiN layer and passivate the oxygen vacancies without increasing the oxide thickness by using PMA with various temperatures. Negative bias instability for pFET is improved, especially for the oxygen annealed one.
28 nm FET high-k/metal gate was formed on bulk Si. After interfacial SiO2 layer/high-k and TiN deposition, TiN layer was then deposited with the thickness of 100~200 Å. The fabrication process of the high-k metal gate last device was sketched in Figure 1. Some of the samples were annealed at 400°C and 450°C in oxygen or nitrogen ambient for several minutes, respectively.
The capacitance-voltage (-) curves were measured with an HP4280 precision LCR meter and the current-voltage (-) curves with an HP-4156B. After the basic electric measurements, the samples were then stressed by using a constant voltage of . After stressing, the samples were measured again to find out the performance of reliability.
3. Results and Discussions
Figure 2 shows the - curves of the samples measured with 1 MHz. The extracted EOT for all samples is about 13 Å. The merged - curves at low voltage for all samples indicate that there is no extra growth in oxide thickness even after 450°C PMA in O2 ambient. Figure 3 shows the - curves for all samples. It could be found that the sample without PMA shows an obviously huge gate leakage current than other samples. On the other hand, the gate leakage current reduced after PMA in all conditions. The reduction of gate leakage current is because of the defects passivation in high-k/Si interface .
Figure 4 shows the - curves for samples with various PMA treatments. It could be observed that the device without annealing shows the most negative threshold voltage due to the existence of charged oxygen vacancy, and the threshold voltage shifts positiveward after PMA treatment. Both the threshold voltages are similar with various annealing temperatures for the nitrogen-annealed devices. On the other hand, the amount of threshold voltage shift of oxygen-annealed device is strongly dependent on the annealing temperature. The positive shift of threshold voltage might be due to the passivation of oxygen vacancies in the interfacial layer (IL) region . Both the oxygen and nitrogen could be permeated through the TiN region and reach the IL region although TiN is commonly used as diffusion barrier. The phenomenon is suggested to reduce the threshold voltage of pMOSFET for the high-performance application.
Figure 5 shows the - curves with various PMA conditions before and after constant voltage stress, and the amount of degradation of was extracted and shown in Figure 6. It could be observed that the device without PMA shows the worst device performance. On the other hand, the reliability is improved for devices with PMA treatment. As compared to the various PMA conditions, the oxygen devices with oxygen annealing show the better reliability than the device with oxygen annealing. The degradation is suggested due to the breaking of passivated oxygen vacancies during stress. Compared to nitrogen, oxygen is believed to cause stronger bonding when passivating the dangling bonds of oxygen vacancies. As a result, the device with oxygen annealing shows the lowest degradation.
In order to realize the mechanism of degradation, the variation of gate leakage current before and after stress was investigated in this work. Figure 7 shows the - curves of samples annealed in N2 ambient at 450°C before and after constant voltage stress. It could be found that the two curves overlap in the region of accumulation and strong inversion, and it divides in the region of depletion and weak inversion. The results could be explained using the following models as shown from Figure 8 to Figure 10. After applying a constant voltage stress, it is believed that some traps would be generated in both interface and high-k dielectric layer. When the device is biased to accumulation (see Figure 8), enough electrons would be injected from the substrate into the gate electrode by tunneling; as a result, the gate leakage current is independent of the generated traps. When the device is biased to depletion and weak inversion (see Figure 9), the gate leakage current includes two components: the generation holes and the gate-injected electrons. The stress-induced traps in the high-k dielectric layer would result in trap assistant tunneling from the gate electrode, and the traps in the high-k/Si interface would enhance the generation holes. Both traps would increase the gate leakage current. In other words, more traps generated in both the gate dielectric layer and the interface would induce larger gate leakage current. As the electric field is large enough (see Figure 10), the electrons and holes would, respectively, pass through conduction band and valance band of the high-k layer. Therefore, the gate leakage current is independent of the stress-induced traps. From the above model, the gate leakage current variation is mainly attributed to both trap assistant tunneling and holes generation in depletion and weak inversion region. As shown in Figure 7, the devices with oxygen annealing have less variation of gate leakage current than those with nitrogen annealing. This could be explained that oxygen annealing has stronger bonding to passivate the dangling bonds of oxygen vacancies, which results in fewer traps generated during stress.
Postmetallization annealing was used in this work to improve the performance and reliability of the high-k/metal gate pMOSFET devices. The models show that the increase of gate leakage current after stress must be due to the traps generation in both high-k gate dielectric layer and high-k/Si interface. It is believed that oxygen would cause the stronger bonding than nitrogen as passivating the dangling bonds of oxygen vacancies. As the results show, the devices with oxygen annealing show the least degradation and gate leakage current variation than the others.
This work was supported by the National Science Council under Contract NSC 100-2221-E-390-004, NSC 100-2221-E-017-002, and the authors would like to thank UMC staff for their helpful supporting.
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