A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS

Table 1

Comparison of the simulation results for different CMOS XOR gates with the proposed XOR gate.

	𝑉dd (v)	Proposed (6T)	6T [5]	6T [4]	4T [6]	4T[7]	3T [1, 9, 10]
	0.6	2.1107	2.3113	7.0638	2.5818	4.1910	15.48
Delay (ns)	0.8	1.5659	1.7672	3.6837	4.5128	3.9308	8.7314
	1	1.4691	1.6475	1.6469	4.2216	8.9244	13.038
	1.2	1.4200	1.6018	1.5500	4.1087	7.2075	12.901
	0.6	0.1351	0.1352	0.1385	0.2672	0.2672	0.2672
Average power (nW)	0.8	0.2312	0.2319	0.2401	0.4586	0.4586	0.4586
	1	0.3674	0.3689	0.3842	0.7269	0.7269	0.7268
	1.2	0.5523	0.5574	0.5835	1.0931	1.0931	1.0928
	0.6	0.2852	0.3125	0.7526	0.6899	1.1198	4.1363
PDP (aJ)	0.8	0.3620	0.4098	0.8845	2.0696	1.8027	4.0042
	1	0.5397	0.6078	0.6327	3.0687	6.4871	9.4760
	1.2	0.7843	0.8928	0.9044	4.4912	7.8785	14.098