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Active and Passive Electronic Components
Volume 2013, Article ID 217674, 9 pages
Research Article

MCML D-Latch Using Triple-Tail Cells: Analysis and Design

1Electronics and Communication Division, Delhi Technological University, Delhi 110042, India
2Electronics and Communication Division, Netaji Subhas Institute of Technology, Delhi 110078, India

Received 25 June 2013; Accepted 17 September 2013

Academic Editor: Ching Liang Dai

Copyright © 2013 Kirti Gupta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18 µm CMOS technology parameters.