MCML D-Latch Using Triple-Tail Cells: Analysis and Design

Table 3

Coefficients of the capacitances for the proposed D-latch.

NMOS coefficients
𝑎db3	2𝐴^2𝑣𝐿MIN/μeff,𝑛𝐶ox(𝑁/(1+𝑁))^2𝐾𝑗𝑛𝐶𝑗𝑛𝐿d𝑛+2𝐾𝑗sw𝑛𝐶𝑗sw𝑛
𝑎gd3	2𝐴^2𝑣𝐶gdo(𝑁/(1+𝑁))^2𝐿MIN/μeff,𝑛𝐶ox
𝑎input	4𝐴^2𝑣/3μeff,𝑛(𝑁/(1+𝑁))^2𝐿MIN^2
𝑐db3	2𝐾𝑗sw𝑛𝐶𝑗sw𝑛𝐿d𝑛
𝑏db3, 𝑏gd3, 𝑐gd3	0
PMOS coefficients
𝑏gd9	(3/4)((1+𝑁)/𝑁)𝐴bulk,maxμeff,𝑝𝐶^2ox𝑊^2MIN𝑉DD−𝑉𝑇,𝑝
𝑐gd9	𝐶gdo𝑊MIN−(3/4)𝐴bulk,maxμeff,𝑝𝐶^2ox𝑊MIN𝑉DD−𝑉𝑇,𝑝𝑅DSW10^−6
𝑐db9	𝐾𝑗𝑝𝐶𝑗𝑝𝐿d𝑝𝑊MIN+2𝐾𝑗sw𝑝𝐶𝑗sw𝑝𝐿d𝑝+𝑊MIN
𝑎gd9, 𝑎db9, 𝑏db9	0

The symbols have their usual meaning.