Additional High Input Low Output Impedance Analog Networks

Abstract

This paper presents some additional high input low output impedance analog networks realized using a recently introduced single Dual-X Current Conveyor with buffered output. The new circuits encompass several all-pass sections of first- and second-order. The voltage-mode proposals benefit from high input impedance and low output impedance. Nonideality and sensitivity analysis is also performed. The circuit performances are depicted through PSPICE simulations, which show good agreement with theory.

1. Introduction

In the recent past, realization of configurable analog networks has assumed special significance for modern analogue signal processing applications. The feature is quite suited while designing analog blocks with easy configurability, so as to be employed in field programmable analog arrays (FPAAs). Simple analog blocks with this feature were reported earlier and further researched in most recent works [1–3]. Whereas configurability gives rise to the possibility of several electronic functions from a single topology, cascadability results in practical utility of analog blocks for designing more complex networks without additional coupling elements in form of buffers [4–6]. The most recent analog circuit topology benefits from these features by being suited for a number of first-order electronic functions and offering high input impedance and low output impedance [5]. The two features together are just another step towards reducing circuit components enabling portable high performance systems with ease for FPAA implementations [7, 8]. It may be noted that analog filters continue to appear in open literature as a potential analog block for larger subsystems [2–6, 9–12].

This paper presents additional first- and second-order all-pass filters with the features of high input and low output impedance. State-of-the-art floating simulators have been employed to overcome the drawbacks of passive inductors [13]. It may be noted that floating inductor simulators using current conveyors have been researched well in the literature [14–17]. Transformation technique has further been employed to realize simpler alternative with lesser circuit complexity. Extensive simulations are performed to validate the proposed theory, which not only justify the proposed theory but also provide advancement to the existing knowledge.

2. Additional First-Order All-Pass Filters

The symbol and CMOS implementation of newly developed second generation Dual-X Current Conveyor (DXCC-II) with buffered output are shown in Figure 1. A newly developed DXCC-II is characterized in matrix form by the following relationship: 𝐼_𝑌𝐼_𝑍+𝐼_𝑍−𝑉_𝑋+𝑉_𝑋−𝑉_𝑊=𝐼000010000100001000−100001^𝑋+𝐼_𝑋−𝑉_𝑌𝑉_𝑍. (1) The new additional voltage-mode first-order all-pass filter topology is shown in Figure 2. It may be noted that interchanging the positions of 𝑋+ and 𝑋− yields the topology of [5], a fact not mentioned therein. The given topology is characterized by the general transfer function for continual signals in “𝑠” domain as 𝑉_𝑜(𝑠)𝑉_𝑖(𝑠)𝑍=−²𝑍₃𝑍₄+2𝑍₁𝑍₂𝑍₃−2𝑍₁𝑍₃𝑍₄𝑍₁𝑍₂𝑍₄+2𝑍₁𝑍₂𝑍₃+2𝑍₁𝑍₃𝑍₄. (2)

(a)

(b)

Figure 1 

(a) Symbol of DXCC-II with buffer, (b) CMOS implementation of DXCC-II with buffer [5].

Figure 2 

Topology extension by interchanging 𝑋 ports of a recent work [5].

Specialization of the impedances in Figure 2 yields missing circuits of voltage-mode first-order all-pass filters as listed in Table 1. The circuits of Filter 1 and Filter 2 use two passive components. In the circuit of Filter 1, 𝑍₂ and 𝑍₄ are retained with 𝑍₂ as a resistor and 𝑍₄ as a capacitor while open-circuiting 𝑍₁ and 𝑍₃. In the circuit of Filter 2, 𝑍₂ and 𝑍₄ are retained with 𝑍₂ as a capacitor and 𝑍₄ as a resistor while open-circuiting 𝑍₁ and 𝑍₃. No matching condition is required in both of the circuits of Filter 1 and Filter 2. In the last two circuits of Filter 3 and Filter 4 three components are used in each case. In the circuit of Filter 3, 𝑍₁, 𝑍₂, and 𝑍₃ are retained with 𝑍₁, 𝑍₃ as capacitors and 𝑍₂ as a resistor while open-circuiting 𝑍₄. In the circuit of Filter 4, 𝑍₁, 𝑍₂, and 𝑍₃ are retained with 𝑍₁, 𝑍₃ as resistors and 𝑍₂ as a capacitor while open-circuiting 𝑍₄. The circuits of Filter 1 and Filter 2 enjoy the advantage of single resistor control. The circuit of Filter 3 also enjoys the feature of single resistor control but is noncanonical. It also employs both capacitors in grounded form. The circuit of Filter 4 is canonical by employing single capacitor but requires matched grounded resistors. It is also to be noted that other useful first-order analog functions (e.g., lossy and loss less integrators, high pass filter, etc.) are also realizable from the modified general topology of Figure 2.

Table 1 

First-order voltage-mode all-pass filters.

3. Second-Order Filters

Selection of the impedances in Figure 2 yields a circuit of second-order voltage-mode all-pass filter by retaining all impedances 𝑍₁, 𝑍₂, 𝑍₃, and 𝑍₄. The selection of impedances is 𝑍₁ and 𝑍₃ as capacitive reactance (𝑍₁=1/𝑠𝐶₁,𝑍₃=1/𝑠𝐶₃,resp.) 𝑍₂ as resistive, and 𝑍₄ is taken as inductive reactance (𝑍₄=𝑠𝐿₄). It is a well-known fact that real inductors are not used in integrated analog systems due to their bulky size, which became a motivating factor for the introduction of active-RC networks long back. In the circuit proposed here, simulated floating inductor [13] is used in place of the real inductor. The DXCC-II based circuit of [13] realizes a resistor less floating inductor. The new proposed voltage-mode second-order all-pass filter using simulated inductance (𝐿₄≡𝐿_sim) is shown in Figure 3(a). Another circuit is obtained by interchanging the positions of the 𝑋+ and 𝑋− terminals and is shown in Figure 3(b). The transfer function of the proposed circuits of Figures 3(a) and 3(b) is given as 𝑉_𝑜(𝑠)𝑉_𝑖(𝑠)𝑠=𝑘²𝐿_sim𝐶₁𝑅₂−2𝑠𝐿_sim+2𝑅₂𝑠²𝐿_sim𝐶₃𝑅₂+2𝑠𝐿_sim+2𝑅₂, (3) where 𝑘=+1 for the circuit of Figure 3(a) and 𝑘=−1 for the circuit of Figure 3(b).

(a)

(b)

Figure 3 

(a)  Proposed second-order all-pass filter using simulated inductor. (b) Another circuit obtained by interchanging 𝑋 ports.

The expressions for pole-𝜔₀ and 𝑄 are given in (4) and (5), respectively: 𝜔₀=2𝐶₃𝐿_sim,𝑄=𝑅₂𝐶₃2𝐿_sim. (4)(5) From (4) and (5), it is found that the 𝑄 can be tuned independent of 𝜔₀ by adjusting the value of 𝑅₂.

Sensitivity figures for pole-𝜔₀ and 𝑄 are given as follows: 𝑆^𝜔0_𝐶3=𝑆^𝜔0_𝐿sim1=−2,𝑆^𝜔0_𝑅2𝑆=0,_𝑄𝑅2=1,𝑆^𝑄_𝐶3=−𝑆^𝑄_𝐿sim=12. (6) From (6), the sensitivity figures for the proposed circuits are found to be less than or equal to unity in magnitude which implies good sensitivity performance.

It is now to be emphasized that inductance simulator value is as 𝐿_sim=(𝐶/𝑔_𝑚1𝑔_𝑚2), where 𝑔_𝑚1 and 𝑔_𝑚2 are transconductance of transistors used in simulated inductor, which can be controlled by the gate voltages of those transistors [13]. Here, 𝑔_𝑚𝑖(𝑖=1,2) is the transconductance of the 𝑖th MOS transistor and is given as 𝑔_𝑚𝑖=2𝜇𝐶_𝑜𝑥𝑊𝐿_𝑖𝑉_𝐺𝑖−𝑉_𝑇𝑖,where𝑖=1,2. (7) By substituting the value of 𝐿_sim in (3), the transfer function becomes 𝑉_𝑜(𝑠)𝑉_𝑖(𝑠)𝑠=𝑘²𝐶𝐶₁𝑅₂−2𝑠𝐶+2𝑅₂𝑔_𝑚1𝑔_𝑚2𝑠²𝐶𝐶₃𝑅₂+2𝑠𝐶+2𝑅₂𝑔_𝑚1𝑔_𝑚2. (8) The expressions for pole-𝜔₀ and 𝑄 are also modified and given in (9) and (10), respectively: 𝜔₀=2𝑔_𝑚1𝑔_𝑚2𝐶₃𝐶,𝑄=𝑅₂𝐶₃𝑔_𝑚1𝑔_𝑚2.2𝐶 (9)(10) Sensitivity figures for pole-𝜔₀ and 𝑄 are now given as follows: 𝑆^𝜔0_{𝑔𝑚1,𝑔𝑚2}=−𝑆^𝜔0_𝐶3=−𝑆^𝜔0_𝐶=12,𝑆^𝜔0_𝑅2𝑆=0,_𝑄𝑅2=1,𝑆^𝑄_𝐶3=𝑆^𝑄_{𝑔𝑚1,𝑔𝑚2}=−𝑆^𝑄_𝐶=12. (11) All the sensitivity figures given in (11) are still less than or equal to unity in magnitude, which suggests good sensitivity performance.

Another possible circuit design is to use frequency transformation method [18]. In frequency transformation, all the impedances are scaled by the frequency-dependent factor 1/𝑠. Such an impedance-level scaling operation is quite appropriate, because this operation does not affect the transfer function. The motivation behind this scaling operation is that scaling inductive impedance 𝑠𝐿 by 1/𝑠 leaves the circuit with the resistor of the same value, 𝑅=𝐿, and the inductor is eliminated. However, so as not to change the transfer function in the scaling operation, all components must be scaled by the same factor. Therefore, the three passive elements are, namely, 𝑍_𝑅=𝑅,𝑍_𝐿=𝑠𝐿,𝑍_𝐶=1().𝑠𝐶 (12) After transformation (1/𝑠) yields the new components 𝑍^′_𝑅=𝑅𝑠,𝑍^′_𝐿=𝐿,𝑍^′_𝐶=1𝑠²𝐶. (13) Such scaling actually results in a transformation of the elements: a resistor (𝑅) becomes a capacitor of value “1/𝑅,” an inductor (𝐿) becomes a resistor of value “𝐿,” and a capacitor (𝐶) becomes a frequency-dependent negative resistor (FDNR) and is denoted by “𝐷” and symbolized as four parallel lines. The resulting circuit after frequency transformation is shown in Figure 4(a). Another circuit is obtained by interchanging the positions of the 𝑋+ and 𝑋− terminals and is shown in Figure 4(b). Here, the active realization of FDNR using DXCC-II may be used [19]. The active realization of FDNR has the advantage of using a single active element and tunability by means of control voltage. The impedance function [19] is given for the ideal case [𝑍]=1/𝑠²𝐷_eq=2/𝑠²𝐶²𝑅 for 𝐶₁=𝐶₂=𝐶.

(a)

(b)

Figure 4 

(a) Proposed second-order all-pass filter using frequency transformation. (b) Another circuit obtained by interchanging 𝑋 ports.

The transfer function of the proposed circuits of Figures 4(a) and 4(b) is given as 𝑉_𝑜(𝑠)𝑉_𝑖(𝑠)𝑠=𝑘²𝐶²₁𝑅₁𝑅₄−4𝑠𝐶₂𝑅₄+4𝑠²𝐶²₃𝑅₃𝑅₄+4𝑠𝐶₂𝑅₄,+4 (14) where 𝑘=+1 for the circuit of Figure 4(a) and 𝑘=−1 for the circuit of Figure 4(b).

The expressions for pole-𝜔₀ and 𝑄 are given in (15) and (16), respectively: 𝜔₀=2𝐶₃𝑅₃𝑅₄,𝐶𝑄=³2𝐶₂𝑅₃𝑅₄. (15)(16) Sensitivity figures for pole-𝜔₀ and 𝑄 are given as follows: 𝑆^𝜔0_𝐶3=−1,𝑆^𝜔0_𝑅3=𝑆^𝜔0_𝑅41=−2,𝑆^𝜔0_𝐶2𝑆=0,_𝑄𝐶2=−𝑆^𝑄_𝐶3=−1,𝑆^𝑄_𝑅3=−𝑆^𝑄_𝑅4=12. (17) From (17), the sensitivity figures for the proposed circuits are all less than or equal to unity in magnitude which implies good sensitivity performance.

As an application of second-order voltage-mode all-pass filter, a sinusoidal oscillator producing two-phase signals is next given. The circuit is shown in Figure 5; it consists of a voltage-mode second-order all-pass filter and a unity gain inverter, with the output of the inverter being fed back to the input of the first stage. It may be noted that the inverter (gain=−1) is realized using DXCC-II itself with input and output at 𝑌 and 𝑋−, respectively. The system loop gain (defined as 𝑉_OUT/𝑉_IN, Figure 5) is given by 𝑉_OUT(𝑠)𝑉_IN(𝑠)=()𝑠−1²𝐿_sim𝐶₁𝑅₂−2𝑠𝐿_sim+2𝑅₂𝑠²𝐿_sim𝐶₃𝑅₂+2𝑠𝐿_sim+2𝑅₂. (18) If loop gain is set to unity at 𝑠=𝑗𝜔, the circuit shown in Figure 5 can be set to provide two-phase sinusoidal oscillation with oscillation frequency as 𝑓₀=1Π2𝐿_sim𝐶₃. (19) The circuit provides two voltage outputs 𝑉_𝑂1 and 𝑉_𝑂2. The voltage outputs marked in Figure 5 are related as 𝑉_𝑂1=−𝑉_𝑂2.

Figure 5 

Proposed voltage mode sinusoidal oscillator.

4. Nonideal Analysis

A nonideal DXCC-II is characterized by the following port relationship: 𝐼_𝑌𝐼_𝑍+𝐼_𝑍−𝑉_𝑋+𝑉_𝑋−𝑉_𝑊=𝛼0000_𝑝0000𝛼_𝑛0000𝛽_𝑝000−𝛽_𝑛0𝐼000𝛾^𝑋+𝐼_𝑋−𝑉_𝑌𝑉_𝑍. (20) Here, 𝛼_𝑝 and 𝛼_𝑛 are the current transfer gains from 𝑋+ and 𝑋− terminals to 𝑍+ and 𝑍− terminals, respectively, 𝛽_𝑝 and 𝛽_𝑛 are the voltage transfer gains from 𝑌 input terminal to 𝑋+ and 𝑋− terminals, respectively, and 𝛾 is the voltage transfer gain from 𝑍+ terminal to 𝑊 terminal (buffered output). However, these transfer gains are close to unity up to very high frequencies [20]. Using (20), the proposed circuits of voltage-mode second-order all-pass filter using simulated inductor as shown in Figures 3(a) and 3(b) are reanalyzed so as to yield the following voltage transfer function: 𝑉_𝑜(𝑠)𝑉_𝑖(𝑠)𝑠=𝑘𝛾²𝛼_𝑝𝛽_𝑝𝐿_sim𝐶₁𝑅₂−𝑠𝐿_sim𝛽_𝑛1+𝛼_𝑛+𝑅₂𝛽_𝑝1+𝛼_𝑝𝑠²𝐿_sim𝐶₃𝑅₂+𝑠𝐿_sim1+𝛼_𝑛+𝑅₂1+𝛼_𝑝, (21) where 𝑘=+1 for the circuit of Figure 3(a) and 𝑘=−1 for the circuit of Figure 3(b).

The expressions for pole-𝜔₀ and 𝑄 are given as follows: 𝜔₀=1+𝛼_𝑝𝐶₃𝐿_sim,𝑅𝑄=²1+𝛼_𝑛𝐶₃1+𝛼_𝑝𝐿_sim. (22) Active and passive sensitivity figures for pole-𝜔₀ and 𝑄 are given as 𝑆^𝜔0_𝐶3=𝑆^𝜔0_𝐿sim1=−2,𝑆^𝜔0_𝑅2𝑆=0,_{𝜔0𝛼𝑝}=𝛼_𝑃21+𝛼_𝑝,𝑆^𝜔0_𝛼𝑛𝑆=0,_𝑄𝑅2=1,𝑆^𝑄_𝐶3=−𝑆^𝑄_𝐿sim=12,𝑆^𝑄_𝛼𝑝=𝛼_𝑝21+𝛼_𝑝,𝑆^𝑄_𝛼𝑛𝛼=−^𝑛1+𝛼_𝑛. (23) Using (20), the proposed circuits of voltage-mode second-order all-pass filter using frequency transformation as shown in Figures 4(a) and 4(b) are reanalyzed so as to yield the following voltage transfer function: 𝑉_𝑜(𝑠)𝑉_𝑖(𝑠)𝑠=𝑘𝛾²𝛼_𝑝𝛽_𝑝𝐶²₁𝑅₁𝑅₄−2𝑠𝛽_𝑛𝐶₂𝑅₄1+𝛼_𝑛+2𝛽_𝑝1+𝛼_𝑝𝑠²𝐶²₃𝑅₃𝑅₄+2𝑠𝐶₂𝑅₄1+𝛼_𝑛+21+𝛼_𝑝, (24) where 𝑘=+1 for the circuit of Figure 4(a) and 𝑘=−1 for the circuit of Figure 4(b).

The expressions for pole-𝜔₀ and 𝑄 are given as follows: 𝜔₀=1𝐶₃21+𝛼_𝑝𝑅₃𝑅₄,𝐶𝑄=³𝐶₂1+𝛼_𝑛𝑅₃1+𝛼_𝑝2𝑅₄. (25) Active and passive sensitivity figures for pole-𝜔₀ and Q are given as 𝑆^𝜔0_𝐶3=−1,𝑆^𝜔0_𝑅3=𝑆^𝜔0_𝑅41=−2,𝑆^𝜔0_𝐶2𝑆=0,_{𝜔0𝛼𝑝}=𝛼_𝑝21+𝛼_𝑝,𝑆^𝜔0_𝛼𝑛𝑆=0,_𝑄𝐶2=−𝑆^𝑄_𝐶3=−1,𝑆^𝑄_𝑅3=−𝑆^𝑄_𝑅4=12,𝑆^𝑄_𝛼𝑝=𝛼_𝑝21+𝛼_𝑝,𝑆^𝑄_𝛼𝑛𝛼=−^𝑛1+𝛼_𝑛. (26) Equation (22) and (26) shows that the sensitivity figures are all less than or equal to unity in magnitude which implies good sensitivity performance. Sensitivity of filter parameters to current transfer gains will remain less than unity for the ideal value of current transfer gains which is equal to unity.

5. Parasitic Considerations

The next study on the proposed circuits is carried out for the effect of parasitics involved with the used current conveyor. It assumes special significance for evaluating the real performance of any analog circuit. The various parasitics involved with a typical current conveyor [21] are well known to potential readers and will only be reviewed briefly. The various parasitics of the DXCC-II used in the proposed circuits are port 𝑍 parasitics in the form of 𝑅_𝑍//𝐶_𝑍, port 𝑌 parasitic in the form of 𝑅_𝑌//𝐶_𝑌 and port 𝑋 parasitics. The proposed circuits are re-analyzed by taking into account the above parasitic effects. A re-analysis of the proposed circuit of voltage-mode second order all-pass filter using simulated inductor as shown in Figure 3(a) yields: 𝑉_𝑜(𝑠)𝑉_𝑖(𝑠)𝑠=−²𝐿_sim𝐶^′₁𝑅^′₂−2𝑠𝐿_sim+2𝑅^′₂𝑠²𝐿_sim𝐶^′₃𝑅^′₂+2𝑠𝐿_sim+2𝑅^′₂, (27) where 𝑅^′₂=𝑅₂+𝑅_𝑋−, 𝐶^′₁=𝐶₁+𝐶_𝑋+, and 𝐶^′₃=(𝐶₃+𝐶_𝑍++𝐶_𝑍−).

From (27), it is clear that the parasitic resistances/capacitances merge with the external value. Such a merger does cause slight deviation in circuit’s parameters. It can be further observed from (27) that the order of transfer function of second-order all-pass filter is not changed. The modified expressions for pole-𝜔0 and 𝑄 with parasitic effects are also given as 𝜔₀=2𝐶^′₃𝐿_sim,𝑄=𝑅^′₂𝐶^′₃2𝐿_sim. (28)(29) Next, it is seen from (28) that the pole frequency would slightly be deviated (in deficit) because of these parasitics. The expression showing the effects of parasitics on pole-𝑄 is also given in (29). The pole-𝑄 would also deviate slightly because of the parasitics. The deviation is expected to be small for an integrated DXCC-II.

6. Simulation Results

The new proposed circuits are verified through PSPICE simulations. The simulations are based on 0.5 𝜇m, TSMC, CMOS parameters. Table 2 shows the dimensions of MOS parameters which are used in CMOS implementation of DXCC-II of Figure 1(b). The supply voltages used are ±2.5 V, 𝑉_𝐵𝐵=−0.6V, 𝐶_𝐶=0.06pF, and 𝐼_𝐵=25𝜇A. The proposed voltage-mode second-order circuit of all-pass filter using simulated inductor has been designed at the pole frequency of 15.92 MHz. For the circuit of voltage-mode second-order all-pass filter (Figure 3(a)) resistance used is 𝑅₂=20KΩ, capacitors used are of values 𝐶₁=𝐶₃=1pF, and, for the resistor less floating simulated inductor, the dimensions of the NMOS transistors are 𝑊/𝐿=2𝜇m/0.5𝜇m. The bias voltages are selected to be 0.78 V so as to obtain a resistance of 20 kΩ across each one of the MOS transistor. The capacitance 𝐶 is set to 2 pF so as to realize a floating inductance of 0.2 mH. The gain and phase response of the circuit of Figure 3(a) are shown in Figure 6, which shows the pole frequency as 15.85 MHz with a percentage error of 0.44%. The usefulness of new circuits is to be especially emphasized keeping in view the design frequency which is quite high. The input-output waveforms for voltage-mode second-order all-pass filter are shown in Figure 7. The Fourier spectrum of output is shown in Figure 8. The THD is found to be 1.5% which is also moderately low. The plot of THD variation at output with the amplitude of the input voltage is shown in Figure 9. Furthermore, the circuit of second-order voltage-mode all-pass filter using FDNR (Figure 4(a)) is also simulated. The gain and phase response of the circuit of Figure 4(a) are given in Figure 10. The circuit of Figure 4(a) was designed using 𝐶₂=10pF, 𝑅₄=4kΩ, and, for the realization of resistor less FDNR, the dimensions of the NMOS transistor are selected as 𝑊/𝐿 = 4 𝜇m/1 𝜇m. The bias voltage is selected to be 1.2 V so as to obtain a resistance of 1.6 kΩ across the MOS transistor. The capacitances are set as 𝐶_𝐷11=𝐶_𝐷12=50pF and 𝐶_𝐷31=𝐶_𝐷32=50pF to realize FDNR1 (𝐷₁) and FDNR3 (𝐷₃), respectively. The theoretical pole frequency used in this design was 25.18 MHz. The simulated pole frequency was found to be 25 MHz, which is very close to the theoretical value and only 0.71% in error.

Table 2 

Dimensions of MOS transistors in DXCC-II of Figure 1(b).

(a)

(b)

Figure 6 

Gain (dB) and phase (deg) response of second-order voltage-mode all-pass filter of Figure 3(a).

Figure 7 

Input/output waveforms at 15.92 MHz.

Figure 8 

Fourier spectrum of output waveform at 15.92 MHz.

Figure 9 

THD variation at output with signal amplitude at 15.92 MHz.

(a)

(b)

Figure 10 

Gain (dB) and phase (deg) response of second-order voltage-mode all-pass filter of Figure 4(a).

The Monte Carlo analysis of the second order voltage-mode all-pass filter (Figure 3(a)) was next performed taking 5% Gaussian deviation in the each passive component (𝐶₁, 𝑅₂, 𝐶₃, and 𝐿_sim). The analysis was done for 5 runs. The gain and phase response with Monte Carlo analysis is shown in Figure 11 and time domain result for Monte Carlo analysis is shown in Figure 12. As depicted from Monte-Carlo analysis results, the proposed filter has good sensitivity performances.

(a)

(b)

Figure 11 

Monte Carlo analysis of Figure 3(a) showing gain (dB) and phase (deg) response.

Figure 12 

Monte Carlo analysis of Figure 3(a) showing output for 5 runs.

7. Conclusion

This work presents four additional voltage-mode first-order all-pass filters and second-order all-pass filters with high input and low output impedance in each case. The circuits are based on the recently introduced active element, namely, Dual-X Current Conveyor with buffered output. As an application of the second-order voltage-mode all-pass filter, a voltage-mode oscillator configuration is given. Nonideal analysis of the proposed circuits is performed, and parasitic considerations are also discussed. The proposed circuits enjoy good active and passive sensitivities. Simulations results are given to confirm the presented theory.

Acknowledgments

The authors thank Academic Editor for recommending this paper. At the time of paper submission, the article processing charges for the Journal were waived off.