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Active and Passive Electronic Components
Volume 2013 (2013), Article ID 725075, 6 pages
Research Article

A 0.8–6 GHz Wideband Receiver Front-End for Software-Defined Radio

1Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
2Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan

Received 8 October 2013; Accepted 15 November 2013

Academic Editor: Ching Liang Dai

Copyright © 2013 Kuan-Ting Lin et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A wideband (0.8–6 GHz) receiver front-end (RFE) utilizing a shunt resistive feedback low-noise amplifier (LNA) and a micromixer is realized in 90 nm CMOS technology for software-defined radio (SDR) applications. With the shunt resistive feedback and series inductive peaking, the proposed LNA is able to achieve a wideband frequency response in input matching, power gain and noise figure (NF). A micromixer down converts the radio signal and performs single-to-differential transition. Measurements show the conversion gain higher than 17 dB and input matching (S11) better than −7.3 dB from 0.8 to 6 GHz. The IIP3 ranges from −7 to −10 dBm, and the NF from 4.5 to 5.9 dB. This wideband receiver occupies 0.48 mm2 and consumes 13 mW.

1. Introduction

Software-defined radio was designed to process any signal within a certain bandwidth [1]. For an SDR in 0.8–6 GHz region, it includes signals of GSM, 3 G, WLAN, Bluetooth, WiMAX, and GPS applications. Such an idea can be realized by using an ultra-high speed ADC for direct sampling, but the power consumption of the high speed ADC is too large to accept. Relatively, a SDR receiver that down-converts signals before ADC appears to be a more practical approach.

The intuitive SDR receiver topology is to connect front-ends of different standards in parallel as shown in Figure 1(a); nevertheless, the chip size of such topology would be too large. A wideband radio [26] and a tunable-band radio [79] (see Figure 1(b)) are good candidates for this purpose. The most challenging problem is how to design an LNA and a mixer that meet all the requirements in such a wideband from 800 MHz to 6 GHz.

Figure 1: (a) Multiband receiver architecture. (b) Wideband or tunable-band receiver architecture.

A wideband RFE can be implemented by several circuit structures. Conventional common-gate LNAs feature wide input matching and gain bandwidths [4]. However, the multiple stages required by such circuits for gain and noise flatness can be power hungry. A shunt-shunt feedback LNA followed by a passive mixer [2, 5, 6] can be an option, but its gain degrades at high frequency due to the large capacitance at its input and output stages. Besides, the trade-off between noise figure and bandwidth remains an issue. Tunable-band receivers switching its frequency with tunable passive devices [79] would be promising, except that the size of passive devices is too costly to accept. Designs of mixers can be also challenging for SDR. Passive mixers are widely used for frequency down-conversion. Very large power is needed for LO input to drive these passive mixers which results in power consumption and interference problems.

In order to solve the above issues, a wideband RFE utilizing a resistive feedback LNA and a micromixer is proposed. This LNA adopts the resistive feedback technique and inductive peaking to extend the bandwidth [10, 11]. The micromixer [1214] topology is used for down-conversion as well as single-to-differential transition in a wide frequency range without the high LO signal power requirement. As a result, this RFE accomplishes the wideband, low power, and small size criteria of SDR applications.

2. Receiver Architecture

Figure 2 shows the block diagram of the proposed SDR system. The receiver comprises a 0.8–6 GHz wideband LNA, two micromixers, baseband blocks, a frequency divider, and an LO signal generator. Requirements of the LNA include flat frequency responses of high gain and low NF, wideband matching, and good phase linearity (i.e., small group-delay variation). After LNA, the micromixers down-convert signal frequency to a lower band for baseband signal processing. In addition, the frequency divider can generate differential LO signals.

Figure 2: Block diagram of SDR receiver.

3. Design of Wideband Receiver Front-End

Figure 3 shows the schematic of the proposed RFE. Resistive feedback and inductive peaking technique are adopted in the LNA. The amplified signal is coupled through a capacitor to a micromixer. Design principles of each stage are described as follows.

Figure 3: Schematic of proposed receiver front-end.

3.1. Wideband LNA

The small-signal model of the proposed LNA is shown in Figure 4, where the equal to is the impedance looking into the input of the LNA after the gate inductor , and equal to () is the input impedance of the micromixer. The input impedance is expressed by (1) with parameters mapping onto Figure 3. Note that represents parasitic capacitance at the input node, and represents the input dc blocking capacitor, As the input impedance of the conventional resistive shunt-shunt feedback amplifier, provides 50 Ω input matching. Since and will affect the low frequency matching, they are chosen to be as large as possible (7 pF and 3 pF, resp.). In order to extend the matching range to higher frequencies, a series inductor is added to generate a dip in the frequency response of input matching (). The dip frequency is determined by and values, which are 1.2 nH and 257 fF, respectively. The input matching of the LNA can be calculated by substituting (1) into (2),

Figure 4: Small-signal model of wideband LNA.

The voltage gain of the LNA, , can be derived and separated by and expressions as illustrated in (3)–(5), where is the capacitance looking into the drain of and is the peaking inductor. Since gain starts decreasing at the frequency () and the degradation becomes even more serious due to the large size of transistors and , is used to resonate out and extend the bandwidth. The sizes of and are of the same size: 32 fingers with a ratio of 8 μm/90 nm per finger. The inductance of is 0.55 nH.

The noise figure of the LNA is derived according to [11]: where represents the source resistance, represents the gate resistance of , represents the source resistance of , epresents the series resistance of the gate inductor, and are the coefficients of gate noise and channel noise, and is the ratio of to zero-bias drain conductance .

Note that affects the input matching, gain, and noise figure. A large improves the gain and noise performance but results in significant variation across the frequency band. To perform the maximum flat frequency response, a resistance of 340 Ω is used.

Apart from bandwidth extension, the resistive feedback topology improves the linearity of the amplifier [15]. However, the improvement can be observed only in the lower frequency range because of the limited feedback loop bandwidth, as will be seen in the measurement results.

3.2. Micromixer

A micromixer possesses wideband input matching, high linearity, and single-to-differential conversion ability, which makes this topology suitable for the proposed SDR application.

Single-to-differential conversion is accomplished by injecting the signal current into the source of transistor and replicating this current to with the opposite current direction. The sizes of transistors are the same and equals to 48 μm/90 nm to balance both paths. Frequency down-conversion is completed by the switching core whose sizes are 90 μm/90 nm. The output load resistor is parallel with to filter out high frequency noise and harmonics. (10.8 pF) and (500 Ω) generate a pole at 29.5 MHz for sufficient IF bandwidth. To ensure the single-to-differential conversion, the operation frequency of the micromixer should be well below the dominant pole frequency, which is contributed by from and from and . For a 90 nm CMOS technology, the cut-off frequency is as high as 80 GHz; therefore, such topology remains suitable in the interested frequency range.

The conversion gain of the micromixer can be derived as (9), assuming the switching pair operates ideally, The noise factor of the mixer can be obtained by [16] and expressed as follows: where and are evaluated with the bias current of each switching pair, and are the noise factor and gate resistance of each transistor, the transconductance of the stage , and the current passing through and . is the amplitude of the LO signal and is the load resistance of the micromixer. When LO amplitude becomes large enough, and start to approach 1 and , respectively. The effect of the LO port and gate resistance in stage is so small that the noise factor can be reduced as (12):

The conversion gain of the RFE can be expressed by the product of (3) and (9) and used in the following discussions. Similarly, the noise performance, dominated by LNA, is derived as (14) according to Friis noise formula for further comparisons,

4. Measurement Results and Discussion

The RFE was realized in 1P9M 90 nm CMOS technology. On-wafer measurement was performed by using an Agilent 8722ES network analyzer for input matching measurements. Signal generators Agilent E8257D and Agilent E4438C are used to provide LO and RF signals, respectively. Spectrum analyzer Agilent E4440A is used for IF spectrum and noise figure measurements.

Figure 5 shows the measured, calculated, and simulated input matching versus frequency characteristics of the RFE. The is below −10 dB in 1.2–8.9 GHz and −7.3 dB in 0.8–1.2 GHz, respectively. The first dip is determined by and at low frequency. The second dip is located by and at high frequency. Figure 6 shows the measured, calculated, and simulated conversion gain versus frequency characteristics of the RFE. The measured conversion gain is larger than 17 dB from 0.8 to 6 GHz owing to the peaking inductor technique. The declining response at lower frequency is due to the finite value of blocking capacitance . Figure 7 shows the measured, calculated, and simulated noise figure versus frequency characteristics of the RFE. The noise figure varies within 5.2 ± 0.7 dB in the covered frequency range.

Figure 5: Input matching of the proposed receiver front-end.
Figure 6: Conversion gain of the proposed receiver front-end.
Figure 7: Noise figure of the proposed receiver front-end.

The input third intercept points (IIP3) are in the range from −10 to −7 dBm over the frequency of interest as shown in Figure 8. As aforementioned, the IIP3 rolls off at higher frequency due to the limited bandwidth of the feedback loop. The power consumption of the LNA and micromixer are 11.5 and 1.5 mW, respectively, under the supply voltage of 1 V. A summary of the implemented and recently reported CMOS wideband and tunable-band RFEs is given in Table 1.

Table 1: Summary of the implemented and recently reported state-of-the-art CMOS wideband and tunable-band receiver front-ends.
Figure 8: IIP3 of the proposed receiver front-end.

The chip area is 0.48 mm2 including testing pads as shown in Figure 9. The off-chip choke inductor can be implemented by integrated passive device (IPD) technique [17] for future integration. In this work, the inductor is replaced by a bias-T to demonstrate the RFE performance.

Figure 9: Chip micrograph.

5. Conclusion

A wideband RFE from 0.8 to 6 GHz is proposed by using a resistive feedback amplifier and a micromixer. The measurement results show a flat and wideband feature in input matching, gain, and noise performance. The proposed RFE features the lowest power consumption (13 mW) among recently reported silicon-based RFEs in 0.8 – 6 GHz range.


The authors are very grateful to United Microelectronics Corporation (UMC), Hsin-Chu, Taiwan, for chip fabrication, and National Nano-Device Laboratory (NDL), Hsin-Chu, Taiwan, for their technical supports. This work was supported by the National Science Council under Grant NSC-98-2221-E-002-155-MY2.


  1. J. Mitola, “The software radio architecture,” IEEE Communication Magazine, vol. 33, no. 5, pp. 26–38, 1995. View at Google Scholar
  2. R. Van De Beek, J. Bergervoet, H. Kundur, D. Leenaerts, and G. Van Der Weide, “A 0.6-to-10GHz receiver front-end in 45nm CMOS,” in Proceedings of the IEEE International Solid State Circuits Conference (ISSCC '08), pp. 128–129, February 2008. View at Publisher · View at Google Scholar · View at Scopus
  3. S. Lee, J. Bergervoet, K. S. Harish et al., “A broadband receive chain in 65nm CMOS,” in Proceedings of the 54th IEEE International Solid-State Circuits Conference (ISSCC '07), pp. 418–419, February 2007. View at Publisher · View at Google Scholar · View at Scopus
  4. R. Bagheri, A. Mirzaei, S. Chehrazi et al., “An 800-MHz-6-GHz software-defined wireless receiver in 90-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2860–2875, 2006. View at Publisher · View at Google Scholar · View at Scopus
  5. X. Wang, J. Sturm, N. Yan, X. Tan, and H. Min, “0.6-3-GHz wideband receiver RF front-end with a feedforward noise and distortion cancellation resistive-feedback LNA,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 2, pp. 387–392, 2012. View at Publisher · View at Google Scholar · View at Scopus
  6. M. Cao, B. Chi, C. Zhang, and Z. Wang, “A 1.2V 0.1-3GHz software-defined radio receiver front-end in 130nm CMOS,” in Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC '11), June 2011. View at Publisher · View at Google Scholar · View at Scopus
  7. V. Giannini, P. Nuzzo, C. Soens et al., “A 2-mm2 0.1-5 GHz software-defined radio receiver in 45-nm digital CMOS,” IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3486–3498, 2009. View at Publisher · View at Google Scholar · View at Scopus
  8. C.-R. Wu, H.-H. Hsieh, L.-S. Lai, and L.-H. Lu, “A 3-5 GHz frequency-tunable receiver frontend for multiband applications,” IEEE Microwave and Wireless Components Letters, vol. 18, no. 9, pp. 638–640, 2008. View at Publisher · View at Google Scholar · View at Scopus
  9. M. Ranjan and L. Larson, “A sub-1mm2 dynamically tuned CMOS MB-OFDM 3-to-8GHz UWB receiver front-end,” in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC '06), pp. 438–445, February 2006. View at Scopus
  10. H.-K. Chen, D.-C. Chang, Y.-Z. Juang, and S.-S. Lu, “A compact wideband CMOS low-noise amplifier using shunt resistive-feedback and series inductive-peaking techniques,” IEEE Microwave and Wireless Components Letters, vol. 17, no. 8, pp. 616–618, 2007. View at Publisher · View at Google Scholar · View at Scopus
  11. H.-K. Chen, Y.-S. Lin, and S.-S. Lu, “Analysis and design of a 1.628-GHz compact wideband LNA in 90-nm CMOS using a π-match input network,” IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 8, pp. 2092–2104, 2010. View at Publisher · View at Google Scholar · View at Scopus
  12. S.-C. Tseng, C. Meng, C.-H. Chang, C.-K. Wu, and G.-W. Huang, “Monolithic broadband gilbert micromixer with an integrated marchand Balun using standard silicon IC process,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 12, pp. 4362–4371, 2006. View at Publisher · View at Google Scholar · View at Scopus
  13. C. Meng, T.-H. Wu, T.-H. Wu, and G.-W. Huang, “A 5.2 GHz 16 dB gain CMFB Gilbert downconversion mixer using 0.35μm deep trench isolation SiGe BiCMOS technology,” in Proceedings of the IEEE MITT-S International Microwave Symposium Digest, pp. 975–978, June 2004. View at Scopus
  14. F. Piazza and Q. Huang, “A high linearity, single-ended input double-balanced mixer in 0. 25μm CMOS,” in Proceedings of the ESSCIRC (ESSCIRC '12), September 1998.
  15. B. G. Perumana, J.-H. C. Zhan, S. S. Taylor, B. R. Carlton, and J. Laskar, “Resistive-feedback CMOS low-noise amplifiers for multiband applications,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 5, pp. 1218–1225, 2008. View at Publisher · View at Google Scholar · View at Scopus
  16. M. T. Terrovitis and R. G. Meyer, “Noise in current-commutating CMOS mixers,” IEEE Journal of Solid-State Circuits, vol. 34, no. 6, pp. 772–783, 1999. View at Publisher · View at Google Scholar · View at Scopus
  17. H.-K. Chen, Y.-C. Hsu, T.-Y. Lin, D.-C. Chang, Y.-Z. Juang, and S.-S. Lu, “CMOS wideband LNA design using integrated passive device,” in Proceedings of the IEEE MTT-S International Microwave Symposium (IMS '09), pp. 673–676, June 2009. View at Publisher · View at Google Scholar · View at Scopus