Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

Abstract

Ultrathin body (UTB) and nanoscale body (NSB) SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46 nm and lower than 5 nm, respectively, were fabricated using a selective “gate-recessed” process on the same silicon wafer. Their current-voltage characteristics measured at room temperature were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a huge series resistance and found that the last one seems more coherent. Then the electrical characteristics of the NSB can be analytically derived by integrating a gate voltage-dependent drain source series resistance. In this paper, the influence of the channel thickness on the series resistance is reported for the first time. This influence is integrated to the analytical model in order to describe the trends of the saturation current with the channel thickness. This modeling approach may be useful to interpret anomalous electrical behavior of other nanodevices in which series resistance and/or mobility degradation is of a great concern.

1. Introduction

Nanoscale silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) based devices are the building blocks of up-to-date systems allowing ultrafast data processing. This is in accordance with efforts to develop new generation of ultra-fast computers based on combined electronic and signal processing on one hand [1] and advanced generations of nanoscale devices (NSB) for communication systems [2, 3] on the other hand. In this paper, we report the influence of the silicon channel thickness on the electrical characteristics of SOI MOSFET NSB, and we present an accurate model permitting to evaluate the series resistance and the saturation current as a function of the thickness or of the gate voltage, when part of the aim is to explain the anomalous transport behavior of the thinner channels having a channel’s thickness as low as 1.6 nm and obtained by a selective gate-recessed process [4].

The excellent control of the short channel effects, achievable by means of UTB SOI MOSFET architectures, makes them good candidates for ultimate nanometrics scale. Consequently, the transport properties’ study of thin semiconductor films has attracted considerable attention in the recent years.

In this paper, we present the influence of the NSB’s channel thickness on the series resistance in order to complete the unified model of the NSB’s electrical characteristics. In addition to last years’ existing knowledge in series resistance, these novel interpretative approach and analytical model can be useful for the prediction of transport phenomena at the nanoscale and the correction of electrical characteristics.

2. Methodology

2.1. SIMOX Preferred Wafer Processing Technology

Several techniques were developed in the past to create silicon-on-insulator (SOI) devices [5–8], since their implementation was found promising [9–11] for ULSI [12], low power [13], military and space [14], and cost reducing [15] applications. Nowadays, SOI wafers are mainly fabricated using the UNIBOND line of SOI wafers and the smart cut process technologies, patented by SOITEC Company, allowing excellent thickness uniformity [16]. However, for this research purpose, the former SOITEC technology called Separation-by-IMplanted-Oxygen (SIMOX) was preferred because of the clear advantage of presenting an initial gradient of the SOI thickness across the same wafer. This desirable gradient is conserved during the processing of the nanoscale body (NSB) devices as shown in Figure 1, in which are presented spectrophotometry measurements of SOI thicknesses gradient across a 2^′′ diameter SIMOX test wafer after thinning using the gate-recessed process. Consequently, it is possible to study the thickness influence on the NSB electrical characteristics. In Figure 2, the tested NSB devices are presented with their respective channel thicknesses ranging from 1.6 to 4.6 nm as measured by spectrophotometry. The accuracy of the critical channel thickness of 1.6 nm was confirmed by in ex situ HRTEM measurement.

Figure 1 

Gradient of SOI thicknesses measured by spectrophotometry across a 2′′ diameter SIMOX test wafer after thinning using the gate-recessed process. The fitting curve here is serving as a visual guide of the thickness distribution.

Figure 2 

Spectrophotometry measurements of the channel thickness performed on the tested dices containing Nano-Scale Body (NSB) devices (from 4.4 to 1.6 nm). The dices were cut from the same 2′′ diameter SIMOX wafer. The accuracy of the measurements is confirmed by inserted HRTEM picture for the smallest channel thickness value (1.6 nm). The fitting is serving as a visual guide of the thickness distribution.

2.2. Accurate Calibration of the Oxidation Furnace

The most challenging step was the accurate controlled thinning process of the SOI layer using local oxidation in the sub 10 nm range of thickness, while the source and the drain regions remained in their original thickness. In order to check the capability of accurate thinning, preliminary tests of thinning were performed in order to reach thicknesses lower than 10 nm, when characterizing the furnace parameters like furnace temperature, duration of the oxidation, and growth rate [17].

2.3. Device Processing Using Recessed-Gate Channel Technology

The local oxidation was performed by using a nitride mask layer of 38 nm (nitride 1) grown on a thin oxide layer (PAD OX) of 15 nm. The role of the pad oxide was to serve as an interface between the nitride and the silicon to prevent mechanical stresses. A first etching of the nitride and pad oxide layer at the extremities of the active region allowed their oxidation into a 700 nm thick field oxide (FOX). A second etching, performed at the center of the nitride region, allowed exposure of the channel region, while the surrounding nitride capped the source and drain areas. Two steps of oxidation were then performed. First, a 75 nm thick sacrificial oxide layer, called channel oxide (CHAN OX), was grown in order to significantly decrease the channel’s thickness to about 10 nm, before removal. The second phase of the oxidation (25 nm thick), called gate oxidation (GOX), was a more accurate step making possible a final nanoscale thickness of the channel, in the range of 1.6 nm to 6.5 nm, and serving as the gate oxide itself, when the thickness distribution uniformity and the Si-SiO₂ interface quality [18] are serving as important parameters [19, 20]. In order to get reference devices, that is, having an initial silicon channel close to 46 nm, the nitride mask was not etched, so the gate insulator layer is made of the 38 nm thick nitride layer deposited on the 15 nm PAD OX layer.

2.4. Fabrication of the Contact Electrodes

Then, a polycrystalline silicon layer of 220 nm was deposited over the gate oxide, oxidized, and patterned to form the gate electrode. Before the source/drain/gate phosphorus implant, a thin layer nitride (nitride 2) of 30 nm was deposited in order to prevent further oxidation of the thin silicon layer during the implant’s thermal annealing. A Plasma-enhanced chemical vapor deposition (PECVD) oxide (silox 2) of 350 nm thickness was deposited followed by an aluminum metallization step to define the contact areas.

2.5. TCAD Simulation of the Device Processing

In order to perform a deeper and accurate analysis of the process limitations, the layers deposition process was translated to a model of the device using TCAD (TSUPREM-4) software. One of the main outputs of the program is the 2D device cross-section, which includes among others the exact boundaries of the various layers of materials in the structure.

In Figure 3, we present a cross-section of the NSB including the source, gate, and drain (resp., S, G, and D) parts and a zoom of the gate-recessed silicon channel. As presented in the upper insert, the active region (source, gate, and drain terminals) which is built of layers described previously, is terminated by aluminum contacts (layer 10) in the vertical axis and limited by field oxide (layer 07) borders in the horizontal axis. The buried oxide (layer 02) is serving as a barrier between the bulk silicon (layer 01) and the gate-recessed silicon channel (layer 03).

Figure 3 

Cross-view of a TCAD (Tsuprem4) simulated nanoscale devices using the gate-recessed channel process. The layers deposition sequence is described in the text.

The lower insert of Figure 3 represents a zoom-in of the gate-recessed channel, when the silicon layer was thinned from 46 nm to 1.6 nm minimal thickness, as confirmed by HRTEM picture in Figure 2. This points out the advantage of the recessed process in which only the silicon channel is thinned, while the source and the drain extensions remain in their original thickness. So the series resistance of the drain and of the source should not be affected a priori by the thinning process.

In addition to Figure 3, presenting a simulated TCAD cross-view of the device layers, a complementary list of the process parameters was presented in summarizing Table 1.

Table 1 

Process parameters for deposited layers.

3. Results

3.1. 𝐼_DS-𝑉_GS Characteristics in the Linear Domain

Using the semiconductor characterization system (SCS-4200) from Keithley Ltd., 𝐼-𝑉 measurements (room temperature, dark conditions) were performed on a selection of four NSB devices (E15, G15, C12, and C03), having the same channel width and length (𝑊/𝐿=80 μm/8 μm) but a channel thickness (𝑡_SI) below 5 nm: 1.6, 2.4, 2.9, and 4.9 nm, respectively. Since the front gate oxide (GOX) thickness is 26 nm, as checked by HRTEM and ellipsometry, the front gate capacitance (𝐶_ox) is evaluated to 138 nF/cm². Back gate contact was kept floating for all devices. The drain currents (𝐼_DS) versus gate voltage (𝑉_GS) characteristics (from −4 to +4 V) were measured in the linear domain (constant low 𝑉_DS=0.1 V) and are presented in Figure 4 for the four NSBs.

Figure 4 

𝐼DS-𝑉GS characteristics measured at 𝑉DS=0.1 V for four NSB devices (dices E15, G15, C12, and C03) having a channel thickness (𝑡SI) of 1.6, 2.4, 2.9, and 4.9 nm, respectively.

By increasing 𝑉_GS from −4 V to −1 V, 𝐼_DS slowly decreases and slightly depends on 𝑡_SI, indicating a leakage phenomenon (negative resistance) similar to the gate-induced drain leakage (GIDL) observed for both classic and SOI-MOSFET devices [21].

For 𝑉_GS from −1 V to −0.5 V, the steep linear increasing observed at least for 𝑡_SI=4.9 nm, which is combined to the low order of magnitude, characteristic of the subthreshold regime. We note that the subthreshold slope is strongly degraded by decreasing the channel thickness.

However, for positive 𝑉_GS values, above the apparent threshold voltage located around −0.5 V, the characteristics are bent and turned into a linear dependence on 𝑉_GS indicating a constant transconductance 𝑔_𝑚 in the whole positive domain of 𝑉_GS. Since our devices are considered as long channel devices (𝐿=8 μm), the effective mobility (𝜇_eff) can be extracted from 𝑔_𝑚 in the linear domain by the following equation based on the classic gradual channel approximation: for𝑉_GS𝑔≥0,_𝑚≡𝜕𝐼_DS,lin𝜕𝑉_GS𝑉DS=𝑊𝐿𝜇_eff𝜕𝑄_𝑛𝜕𝑉_GS𝑉_DS∼𝑊𝐿𝜇_eff𝐶_ox𝑉_DS,so𝜇_eff=𝐿𝑔_𝑚,lin𝑊𝐶_ox𝑉_DS. (1)(2)

According the extracted values 𝑔_𝑚 from Figure 4 for 𝑉_DS=0.1 V and for other 𝑉_DS values (lower than 0.5 V to stay in the linear domain), we can estimate the effective mobility (𝜇_eff) independently of 𝑉_GS and 𝑉_DS for the four NSBs as seen in Figure 5.

Figure 5 

Extracted transconductance 𝑔𝑚 and effective mobility 𝜇eff versus 𝑉DS for four NSB devices (dices E15, C12, G15, and C03) having a channel thickness (𝑡SI) of 1.6, 2.4, 2.9, and 4.9 nm, respectively. 𝑔𝑚 is extracted from Figure 4 as the slope of the 𝐼DS-𝑉GS for positive 𝑉GS.

Surprisingly the values were found lower than 10 cm²/𝑉_𝑠 and weakly decreasing with 𝑡_SI. However, as far as we know, such a low order of magnitude was never reported in the main works dealing with sub 5 nm nanoscale SOI-MOSFET devices [22–24]. Moreover, the effective mobility is expected to decrease at low and high effective field values (due to the interface scattering degradation factor [25]), so 𝑔_𝑚 should decrease with 𝑉_GS and not be a constant with 𝑉_GS as seen from Figure 4.

3.2. Effective Mobility versus Series Resistance at Zero 𝑉_GS

The electron mobility in similar SOI-MOSFETs is known to be strongly degraded by decreasing the channel thickness below 5 nm. Several important works have attributed the degradation to a combination of Coulomb scattering generated by surface states [23], surface roughness [24–26], and enhanced phonon [27] scattering mechanisms. According to [23], the surface roughness is described as a quantum effect mechanisms dominating at low temperature but strongly dependent on the channel thickness 𝑡_SI below 4 nm even at room temperature. The mobility is found to decrease theoretically as a 𝑡⁶_SI law.

Such a discrepancy with our extracted effective mobility behavior inclined us to interpret our measurements in terms of a parasitic drain-source series resistance that overwhelm the intrinsic channel conductance 𝑔_𝑑 and “screen” the previously cited scattering mechanisms.

Indeed, it is well established that if source drain series resistance 𝑅_SD0 competes with the channel conductance a decreasing of the drain current can be measured [28]. In the linear domain, at zero 𝑉_GS, the drain current can be described by the following equation: For𝑉_GS=0≥𝑉_𝑇,𝐼_DS,lin=𝑔_𝑑1+𝑔_𝑑𝑅_SD0𝑉_DS⟶𝑉_DS𝑅_SD0for𝑔_𝑑≪𝑅_SD0, (3) where 𝑔_𝑑 is the conductance of the channel.

Thus, by dividing the 𝑉_DS fixed value (0.1 V) by the intercept value of 𝐼_DS at zero 𝑉_GS a very large series resistance (𝑅_SD0) can be calculated. By varying 𝑉_DS for low values (below 0.4 V), we got a linear dependence of 𝐼_DS with 𝑉_DS at zero 𝑉_GS, that is, confirmed explicitly by (3).

In Figure 6, the 𝑅_SD0 values, as extracted from Figure 4, and 𝜇_eff, evaluated from (1), are plotted versus the four selected channel thicknesses. The classic 𝑅_SD0 vs. 1/𝑡_SI hyperbolic decay due to the current spreading is plotted for reference but could not match the extracted values. As seen in the same figure, the best fit is found exponential as follows: 𝑅_SD0=𝑅^∗_SD0𝑒^{−𝑡SI/𝑡0} (4) with 𝑅^∗_SD0=4.54 MΩ and 𝑡₀=1.03 nm.

Figure 6 

Semilog plot of 𝑅SD0 and 𝜇eff versus channel thickness for four NSB devices (dices E15, C12, G15, and C03) having a channel thickness (𝑡SI) of 1.6, 2.4, 2.9, and 4.9 nm, respectively. 𝑅SD0 is extracted from Figure 4 as the ratio of the 𝑉DS constant value (0.1 V) to the drain current measured at zero 𝑉GS. 𝜇eff is extracted from (2).

In Figure 6, the 𝜇_eff dependence on 𝑡_SI is found to be far from the theoretical 𝑡⁶_SI dependence due to the roughness scattering [23, 24]. Moreover, the remote Coulomb scattering due to interface charges and reported to decay exponentially with 𝑡_SI in the subdeca-nanometer range [25] cannot match the extracted values of 𝜇_eff. The interpretation of 𝑅_SD dependence with 𝑡_SI will be examined later in the paper (Section 4).

3.3. Extraction of the Series Resistance Degradation Factor with 𝑉_GS

In Figure 4, for positive 𝑉_GS values, the linear trend of 𝐼_DS with 𝑉_GS can be described by the following expression: For𝑉_GS>0,𝐼_DS,lin=𝑉_DS𝑅_SD0+𝑔_𝑚𝑉_GS. (5) We can generalize (3) using a 𝑉_GS dependent series resistance 𝑅_SD. Since in the linear domain, 𝐼_DS,lin has a Ohmic behavior with 𝑉_DS, and the 𝑅_SD expression can be extracted (5) as For𝑉_GS𝐼>0,_DS,lin≡𝑉_DS𝑅_SD⟹𝑅_SD=𝑅_SD01+𝑔_𝑚𝑅_SD0/𝑉_DS𝑉_GS≡𝑅_SD01+𝜃𝑉_GS, (6) where 𝜃 is the series resistance degradation factor (units V⁻¹).

The decreasing of 𝑅_SD at high positive 𝑉_GS has been already observed in classic MOSFET and LDD device [29, 30]. Consequently, 𝜃 can be extracted from 𝑔_𝑚 for a given 𝑅_SD0 and 𝑉_DS from Figure 4. In Figure 7, 𝜃 is plotted versus the four selected channel thicknesses.

Figure 7 

plot of theta versus the four channel thicknesses.

An hyperbolic fit best fit the 𝜃 decay with the channel thickness as follows: 𝜃𝜃=^∗𝑡_SI (7) with 𝜃^∗=1.1 nm ⋅ V⁻¹.

Finally, the drain-source series resistance can be expressed by the following expression depending on 𝑡_SI and 𝑉_GS: 𝑅_SD=𝑅^∗_SD0𝑒^{−𝑡SI/𝑡0}1+𝜃^∗𝑉_GS/𝑡_SI. (8)

3.4. 𝐼_DS-𝑉_DS Characteristics and Model of the Saturation Current for NSB

In Figure 8 we present the measured 𝐼_DS-𝑉_DS characteristics (sweeping 𝑉_DS from 0 to 15 V) for 𝑉_GS=4V for NSB having, respectively, a channel thickness of 4.9 and 1.6 nm. On the one hand, for a given 𝑉_GS, the saturation current is decreased by decreasing the channel thickness 𝑡_SI. On the other hand, for a given 𝑉_GS, the saturation voltage is almost constant by decreasing the channel thickness. We propose a model to describe these saturation trends with 𝑡_SI.

Figure 8 

Measured 𝐼DS-𝑉DS characteristics for NSB’s thickness for four NSB devices (dices E15, C12, G15, and C03) having a channel thickness (𝑡SI) of 1.6, 2.4, 2.9, and 4.9 nm, respectively.

3.5. Dependence of the Saturation Current 𝐼_DS,sat on the Channel Thickness 𝑡_SI for NSB

Assuming that, for a given 𝑉_GS, the variation of the NSB’s saturation voltage 𝑉_DS,sat is mainly due to the 𝑅_SD drop voltage, and we can write the following: Δ𝑉_DS,sat≈Δ𝑅_SD𝐼_DS,sat. (9)

Since the variation of 𝑉_DS,sat is found weak with the 𝑡_SI especially below 4 nm, we can derive from (9) Δ𝑉_DS,sat≈0⟹𝑅_SDΔ𝐼_DS,sat≈−𝐼_DS,satΔ𝑅_SD⟹Δ𝐼_DS,sat𝐼_DS,sat≈−Δ𝑅_SD𝑅_SD. (10)

From (8) we can approximate (10) for 𝑉_GS=4V and low 𝑡_SI by Δ𝑅_SD𝑅_SD𝑡≈−^SI𝑡₀. (11)

By integrating (10) for 𝑉_GS=4V we get finally the modeled saturation current as function of the channel thickness 𝑡_SI according to 𝐼_DS,sat𝑉_GS=4V∼𝐼₀𝑉_GS=4V⋅𝑒^𝑡SI/𝑡0. (12) In Figure 9, the modeled saturation current from (12) is plotted versus the channel thickness for NSBs. We can notice a good agreement with the measured saturation current (for 𝑉_DS=15 V and 𝑉_GS=4 V) for the different NSB’s channel thicknesses.

Figure 9 

Measured saturation current (for 𝑉GS=4 V and 𝑉DS=15V) versus channel thickness for NSB devices and fitted by the model given by (12).

4. Complementary Results for the Elucidation of Series Resistance

In order to corroborate our interpretation and to discriminate it from the carrier mobility, we added several results based on the classic 𝑅_𝑚-𝐿 technique [31, 32] and the gate-to-channel capacitance measurement (or “split 𝐶-𝑉” method) [33]. 𝑅_𝑚 is the measured resistance of the device defined by the reciprocal slope of the 𝐼_DS-𝑉_DS linear characteristics, that is, 1/𝑔_𝑑. We compared the measurements between two kinds of devices: NSB devices having a channel thickness of 1.6 nm and reference UTB devices, having a 46 nm channel thick. The channel width is fixed to 80 μm.

4.1. 𝑅_𝑚-𝐿 Technique

In Figure 10, we compared for both the devices, the measured 𝑅_𝑚 taken at different gate lengths (𝐿=6 μm, 8 μm, and 100 μm), and for different positive gate voltages (𝑉_GS=0 V, 1 V, and 4 V). For the UTBs, 𝑅_𝑚 exhibits a linear growth trend with 𝐿, and a decreasing trend with 𝑉_GS as expected from the classic MOSFET channel resistance [31, 32]. Surprisingly, for NSB devices, 𝑅_𝑚 is found almost constant with 𝐿. This result indicates that the contribution of the channel resistance 𝑅_ch may be negligible for our devices. Assuming that 𝑅_𝑚 is a serial association of 𝑅_ch with the series source-drain resistance 𝑅_SD, 𝑅_𝑚 can be then approximated by 𝑅_SD.

Figure 10 

Comparison of the measured resistance 𝑅𝑚 for NSB’s devices having a channel thickness of 1.86 nm, with UTBs devices (46 nm channel thick), as function of channel length (𝐿) and several 𝑉GS positive values.

Moreover, as seen in Figure 10, for NSB devices, 𝑅_𝑚 is found decreasing with 𝑉_GS. This is consistent with the trend already described in (6) for 𝐿=8 μm. Therefore, these results indicate that the NSB resistance is not related to the intrinsic channel resistance but is apparently overwhelmed by an external series resistance that is almost independent of 𝐿. Although, series resistance is usually an association of contributions such as sheet contact resistance, spreading resistance, and other “wire resistance” [34, pages 223–225], none of these contributions exhibits the strong channel dependence like what is observed here. In our case, the measures resistance should be related to another scattering phenomenon.

4.2. Gate-to-Channel Capacitance 𝐶_GC versus Gate Voltage 𝑉_GS

In order to investigate the contribution of the inversion layer of the channel to the electrical conduction of the NSB, the gate-to-channel capacitance (𝐶_GC) were measured versus 𝑉_GS for two frequencies (𝑓=100 kHz and 𝑓=1 MHz) and compared to UTB’s results. In this setup, the drain and source contacts are connected together to the voltage supply, while the substrate contact is grounded to shunt the source-substrate and drain-substrate capacitances. As presented in Figure 11, it clearly appears that below the threshold voltage 𝑉_𝑇 (about −0.5 V) the UTB’s gate-to-channel capacitance is limited by a large overlap (or fringing) capacitance 2𝐶_ov of about 4.5 pF and 3.9 pF at 1 MHz and 100 kHz, respectively. The overlap or fringing regions are located at the channel edges and/or the source and drain extension regions beside the channel. The positive shift of the capacitance with the frequency may be due to the influence of the cable capacitance on the offset capacitance value (significant at 1 MHz). Above 𝑉_𝑇, 𝐶_GC increases and saturates, since the contribution of the channel capacitance (𝐶_CH) is increasing and gets into its strong inversion value as observed in SOI-MOSFET [35]. However, the hump amplitude (0.4 pF) is found lower than the value expected for the UTB’s front gate capacitance (0.8 pF). The similitude of the UTB curves for the both frequencies shows that the interface traps below the gate are not responding and then are negligible for these devices.

Figure 11 

Representation of the gate-to-channel capacitance 𝐶GC as a function of the 𝑉GS voltage for UTB and NSB devices (at 100 kHz and 1 MHz).

For the NSB device having the same dimensions than the previous UTB (𝑊/𝐿=80/8 (μm)) but a channel thickness as low as 1.4 nm and below 𝑉_𝑇, 𝐶_GC is also limited by a large overlap (or fringing) capacitance 2𝐶_ov (both extensions regions) of about 6 pF and 7.3 pF at 1 MHz and 100 kHz, respectively. The small difference of 𝐶_ov between NSB and UTB may be due to the additional parasitic capacitance due to the thinning process. Like UTB’s 𝐶_GC increases and saturates with hump amplitude of 0.7 pF still lower than the expected value for the NSB’s front gate capacitance (0.9 pF). However, 𝐶_GC steeply decreases for positive 𝑉_GS before saturating to a value lower than the initial 2𝐶_ov value. Moreover, the 𝐶_GC maximum at zero 𝑉_GS (contribution of the channel) decreases strongly by increasing the frequency from 100 kHz to 1 MHz. This frequency dependence could be explained by the presence of charged interface states that contribute to an additive capacitive component to 𝐶_GC at lower frequency [34, 35]. This is corroborated also by the degradation of subthreshold slope, as seen in Figure 4 and by the negative voltage threshold that makes our devices to be “depletion type” devices. These interface traps, located below the gate and at the upper silicon/silicon oxide interface, may be introduced during the thinning (oxidation) step of the gate-recessed process. Consequently, these trapped charges may also contribute to the Coulomb scattering as mentioned above [23] and contribute to the exponential decay of the measured resistance.

In order to check the influence of a huge series resistance on the previous 𝐶_GC-𝑉_GS graph a serial load resistance of 1 MΩ is connected between the voltage supply and the UTB’s source. From Figure 11, we can see that the capacitance hump is drastically reduced (to 0.05 pF) for both frequencies as expected from the capacitance relationship with series resistance assuming a parallel equivalent circuit [34, pages 88–90]. The overlap capacitance is reduced to 1.5 pF (compensated in the graph for comparison sake with unload UTB). So the series resistance may explain the decreasing of 𝐶_GC in the 0-1 V range for NSB devices in particular at 1 MHz but less at 100 kHz. One can interpret this difference by the fact that the surfaces states are more responsive at lower frequency and consequently could “shield” the series resistance effect. Moreover, since 𝑅_SD is decreasing with 𝑉_GS, its influence weakens at higher 𝑉_GS values, so it may explain the increase of 𝐶_GC at 𝑉_GS higher than 1 V at 1 MHz for NSB devices.

4.3. Mobile Charge Density and Effective Mobility Dependence with 𝑉_GS

The mobile charge density 𝑄_𝑛 (𝐶/cm²) of the channel can be evaluated by integrating the previous curves 𝐶_GC-𝑉_GS after subtracting the 2𝐶_OV values (to extract the channel contribution 𝐶_CH) and by normalizing to the gate area (80 μm × 8 μm). In Figure 12, 𝑄_𝑛 is plotted versus 𝑉_GS for UTB and NSB at 100 kHz and 1 MHz. While for UTB, the mobile charge density is increasing linearly in strong inversion (above 𝑉_𝑇), and it is decreasing steeply and vanishing for NSB. By combining 𝑄_𝑛 with the measured conductance (1/𝑅_𝑚) for a given 𝑉_GS, we can extract the effective mobility according to [34, page 541] 𝜇_eff=𝐿𝑊⋅1𝑅_𝑚⋅1𝑄_𝑛. (13)

Figure 12 

Representation of the mobile charge density 𝑄𝑛 as a function of the 𝑉GS voltage for UTB and NSB devices (at 100 kHz and 1 MHz).

For UTB, the mobility values extracted from (13) are compatible with the universal mobility curve [34, page 546] with an order of magnitude of 1000 cm²/Vs. However, for NSB, the effective mobility values are smaller than 5 cm²/Vs (but almost constant) with VGS in the 0–1.5 V range at 100 kHz (see insert in Figure 11). For 1 MHz, effective mobility is increasing with 𝑉_GS. These mobility values are compatible to these extracted. As already mentioned above, this value is a too low value compared to literature for the same kind of devices. Moreover, the increase of 𝜇_eff at high 𝑉_GS values observed for both frequencies is not compatible with the expected degradation of the mobility at high effective field as reported in the literature [21–27]. This reveals the limitation of the mobility extraction method based on the 𝐶-𝑉 analysis in case of strong series resistance dependent on gate voltage. Consequently, in our case, the interpretation of the anomalously low conductance of the NSB relative to UTB could be better described by a series resistance model rather than by a conducting inverted channel for positive 𝑉_GS values. Another explanation of the exponential decay of the 𝑅_SD0 with 𝑡_SI may be related to a quantum “skin-effect” phenomenon due to the electron wave function penetration at the oxide-channel interfaces [36], but here the trapping charge and coulomb scattering seem to better match our results.

5. Conclusion

Nanoscale SOI MOSFET devices were fabricated using a selective recess gate thinning process to get channel thicknesses scaling from 4.9 nm down to 1.6 nm. The electrical characteristics were measured and interpreted as a gate controlled series resistance. The resistance is found to decay exponentially with the channel thickness. An analytical model of the saturation current for the nanoscale devices was extracted accordingly. The model is found satisfying to fit the exponential dependence of the measured saturation current with the channel thickness. As suggested by the 𝐶-𝑉 dependence on frequency, this degradation may be related to a high charge density trapped at the channel-gate oxide interface. We admit that the exact origin of the conductance degradation is not trivial and more in depth work is needed. But, in our case, the series resistance interpretation was found more physically coherent than the extraction of the effective channel mobility from the split 𝐶-𝑉 technique that may lead to erroneous values and anomalous trends with 𝑉_GS.

Conflict of Interests

The authors have no conflict of interests associated with this paper.

Acknowledgment

The authors would like to acknowledge the assistance of Albert Ciprut in the TCAD simulation work.