New Realizations of Single OTRA-Based Sinusoidal Oscillators

Abstract

This study proposes three new sinusoidal oscillators based on an operational transresistance amplifier (OTRA). Each of the proposed oscillator circuits consists of one OTRA combined with a few passive components. The first circuit is an OTRA-based minimum RC oscillator. The second circuit is capable of providing independent control on the condition of oscillation without affecting the oscillation frequency. The third circuit exhibits independent control of oscillation frequency through a capacitor. This study first introduces the OTRA and the related formulations of the proposed oscillator circuits, and then discusses the nonideal effects, sensitivity analyses, and frequency stability of the presented circuits. The proposed oscillators exhibit low sensitivities and good frequency stability. Because the presented circuits feature low impedance output, they can be connected directly to the next stage without cascading additional voltage buffers. HSPICE simulations and experimental results confirm the feasibility of the new oscillator circuits.

1. Introduction

Sinusoidal oscillators constitute an important unit in numerous electronic devices, including electronic instruments, measurement systems, telecommunications, power conversion control circuits, and signal processing applications [1]. For the past several years, the typical configurations of sinusoidal oscillators in a wide array of circuit systems have combined operational amplifiers (op-amp) and additional passive components. A variety of sinusoidal oscillators using an op-amp as the active device are available [2, 3]. However, the finite gain bandwidth product of an op-amp decreases the oscillator circuit performance. To overcome this problem, researchers have investigated current-mode circuit techniques for signal processing in the past decades because they offer the advantages of greater accuracy, wider bandwidth, and higher slew rate than their voltage-mode counterparts [4]. Previous studies present several implementations of sinusoidal oscillators employing current conveyors (CCs) and current feedback amplifiers (CFOAs) [5–8], and the literature contains numerous sinusoidal oscillators constructed with different types of modern active devices [9–12]. Since the introduction of OTRA in 1992, it has become an important building block in analog circuit designs [13]. Subsequent development led to two high-performance CMOS OTRA realizations [14, 15]. OTRA can also be implemented using commercially available ICs [16], and has sparked interest in the design of OTRA-based analog signal processing circuits. Several oscillator circuits based on OTRAs have been presented [17–21]. To our knowledge, the first reported oscillator circuits using OTRA as the active device appeared in [17]. That study first introduced three single OTRA-based oscillator circuits and then four additional topologies using two OTRAs. However, the main disadvantage of these circuits is that they require excessive active devices and passive components. To overcome this problem, an improved topology built with a single OTRA, three resistors, and two capacitors was subsequently reported to reduce the component count [18]. Recent research presents an OTRA-based oscillator with noninteractive control [19]. However, that design suffers from complex circuitry involving two OTRAs, three resistors, and three capacitors. A literature review presents other types of sinusoidal oscillators, such as quadrature oscillators and multiphase oscillators, that use OTRA as the active device [20, 21]. Previous study revealed that an available method for generating quadrature oscillators is based on the cascaded all-pass filters technology [20, 22, 23]. Although single OTRA-based sinusoidal oscillators appear in previous reports, a number of effective topologies are missing in the literature. Therefore, the main purpose of this paper is to add three unpublished schemes to this list. One OTRA with a few passive components is required for the three topologies in this study. Because the OTRA-based application circuits got more and more attentions, we believe that these brand-new circuit configurations can be a good alternative to exploit OTRA for the design of sinusoidal oscillators. To illustrate the novelty of the proposed topologies, comparisons of various solutions are shown in Table 1. It should be noted that among the existing circuits, the proposed oscillators in this study feature the following benefits: (1) fewer or the same number of active devices and passive components is used; (2) independent control on the oscillation condition (oscillation frequency) without affecting the oscillation frequency (oscillation condition); (3) low active and passive sensitivities; (4) good frequency stability; (5) insensitive to the parasitic parameters; and (6) without an additional buffer for cascading applications. This paper is organized as follows. Section 2 first introduces the active OTRA device and then explains and analyzes the proposed circuits. Section 3 investigates the nonideal effects, sensitivity analysis, and frequency stability of the proposed circuits. Section 4 describes how examples were made for conducting simulation and experimental tests. Section 5 presents conclusions.

Table 1 

Comparisons among various sinusoidal oscillators.

2. Circuit Descriptions

The OTRA design concept originated from the commercially available Norton amplifier [24, 25]. However, the Norton amplifier has not gained considerable attention because commercially products do not provide a virtual ground at the input terminals and they only allow the input currents to flow in one direction. These adverse conditions limit its applications. Therefore, an improved design was suggested and renamed as operational transresistance amplifier (OTRA) [13]. The OTRA is a trans-impedance type active building block with two current input terminals (𝐼₊ and 𝐼₋) and a voltage output terminal (𝑉_𝑜), which means that the input currents control output voltage through a transresistance gain. Figure 1 shows a circuit diagram of the OTRA used in this study. Its terminal relationships can be defined by (1), where 𝑅_𝑚 represents the transresistance gain. In the ideal case, the transresistance gain 𝑅_𝑚 approaches infinity and the two input currents are forced to be equal. However, this would only happen when OTRA is used in closed feedback loop and the infinite feedback loop gain ensures this. Since the input terminals of OTRA are internally grounded, this active device is free from numerous parasitic effects [26]. Another advantage of using OTRA to design analog circuits is that it is possible to obtain very accurate transfer functions in cascading applications [20]: 𝑉₊𝑉₋𝑉_𝑜=𝑅000000_𝑚𝑅_𝑚0𝐼₊𝐼₋𝐼_𝑜. (1)

Figure 1 

OTRA circuit diagram.

Figure 2 depicts a feasible CMOS OTRA consisting of a differential current controlled current source (DCCCS) followed by a voltage buffer [15]. The DCCCS unit in this figure is based on transistors 𝑀₁ to 𝑀₁₂, and 𝑀₁₃ to 𝑀₂₀ form the voltage buffer. Furthermore, the OTRA can be easily implemented using commercially available ICs with a configuration consisting of two AD844ANs [16] (Figure 3). If terminal 𝑇_𝑧 of the second AD844AN is an open circuit, the precise behavior of an ideal OTRA can be determined. Because the AD844AN IC is widely used in a variety of analog circuits, the implementation depicted in Figure 3 provides a viable means with which to implement an OTRA even though such a device is not currently available.

Figure 2 

CMOS implementation of OTRA.

Figure 3 

OTRA constructed using commercially IC AD844ANs.

Figure 4 shows the proposed new oscillators. Each circuit consists of a single OTRA and a few passive components. Since the minimum passive component sinusoidal oscillators have received much interest in the literature [27, 28], this study first introduces a 2𝑅+2𝐶 topology to fulfill the minimum RC component design (Figure 4(a)). Assuming an ideal OTRA characterized by (1), routine circuit analysis yields the characteristic equation expressed in (2). Equations (3) and (4) determine the oscillation condition and oscillation frequency, respectively. The oscillation condition and oscillation frequency cannot be independently controlled on this circuit because it is a minimum RC oscillator: 𝑆²𝐶₁𝐶₂+𝑆𝐺₁𝐶₂+𝐺₁𝐶₁−𝐺₂𝐶₁+𝐺₁𝐺₂𝐺=0,₂𝐺₁𝐶−1=²𝐶₁,𝜔_𝑜=𝐺₁𝐺₂𝐶₁𝐶₂. (2)(3)(4)

(a)

(b)

(c)

Figure 4 

Circuit diagrams of the proposed single OTRA-based sinusoidal oscillators.

To achieve independent control of the oscillation condition without affecting the oscillation frequency, the second topology employs one OTRA with three resistors and two capacitors (Figure 4(b)). Equations (5) to (7) derive the expressions of the characteristic equation, oscillation condition, and oscillation frequency for this circuit. Among them, 𝐺₁, 𝐺₂, and 𝐺₃ represent the corresponding admittances of the resistors 𝑅₁, 𝑅₂, and 𝑅₃, respectively. Equations (6) and (7) show that the admittance 𝐺₃ can control the oscillation condition without affecting the oscillation frequency: 𝑆²𝐶₁𝐶₂+𝑆𝐺₁𝐶₁+𝐺₂𝐶₁+𝐺₃𝐶₁−𝐺₁𝐶₂+𝐺₁𝐺₂𝐺=0,1+²𝐺₁+𝐺₃𝐺₁=𝐶₂𝐶₁,𝜔_𝑜=𝐺₁𝐺₂𝐶₁𝐶₂. (5)(6)(7)

It is also possible to achieve independent control of the oscillation frequency without affecting the oscillation condition. In this case, Figure 4(b) shows that changing the resistor 𝑅₃ to be a capacitor 𝐶₃ yields the third topology, shown in Figure 4(c). Routine circuit analysis shows that the characteristic equation, oscillation condition, and oscillation frequency of this circuit are expressed as 𝑆²𝐶₁𝐶₂+𝐶₃+𝑆𝐺₁𝐶₁+𝐺₂𝐶₁−𝐺₁𝐶₂+𝐺₁𝐺₂𝐺=0,1+²𝐺₁=𝐶₂𝐶₁,𝜔_𝑜=𝐺₁𝐺₂𝐶₁𝐶₂+𝐶₃. (8)(9)(10)

This oscillator can be considered a single capacitor-controlled oscillator (SCCO) because the oscillation frequency can be controlled independently by 𝐶₃. The presented scheme in this study provides a more compact circuit topology than the previous design (single capacitor-controlled oscillator) reported in [17]. However, typical single capacitor-controlled oscillators cannot provide an excellent tuning capability for the oscillation frequency. To attain a high tuning capability of the oscillation frequency, a tunable capacitor simulated circuit can be applied to overcome this problem [29]. Compared with the topologies reported in [17] [Figures 3(b) and 3(c)], the proposed oscillators use relatively few passive components to realize the topologies for the independent control of the oscillation condition and oscillation frequency. Because OTRA-based application circuits have received more attention in recent years, the proposed oscillator circuits can serve as practical designs for apply in the OTRA circuit systems.

3. Nonideal Analysis of the Proposed Circuits

This section considers several nonideal characteristics to determine the influences of nonideal effects on the proposed circuits. According to the datasheet [30], show that an AD844AN IC can be modeled as a positive second-generation current conveyor (CCII+) cascading a voltage buffer with inherent parasitic resistances and finite tracking errors. Figure 5 reveals a more sophisticated circuit model of the OTRA (Figure 3), where 𝑅_𝑥 and 𝑅_𝑧 are the terminal parasitic resistances. In this design, 𝑅_𝑥 is on the order of several tens of ohms, whereas 𝑅_𝑧 is in the range of a few mega-ohms. 𝛽 represents the current tracking error factor from terminal 𝑇_𝑧 with respect to the inverting terminal. The AD844AN datasheet indicates that the standard values of these parameters are 𝛽=0.98, 𝑅_𝑥=50 Ω, and 𝑅_𝑧=3 MΩ. Figure 5 includes the resulting expressions of the related currents. The parasitic resistance at the noninverting terminal and voltage tracking error effect between the inverting and noninverting terminals of CCII+ both disappear in the circuit model because of the ground connection at the noninverting terminal for each CCII+.

Figure 5 

Equivalent circuit model of the OTRA (Figure 3) with nonideal and parasitic effects.

After applying the nonideal OTRA equivalent circuit model to the proposed circuits shown in Figure 4, tedious derivations lead to the following modified characteristic equations, oscillation condition, and oscillation frequency. The characteristic equation of Figure 4(a) becomes 𝑆²𝐶₁𝐶₂𝐺𝛽+^𝑧𝐺_𝑥+𝑆𝛽𝐺₁𝐶₁+𝛽𝐺₁𝐶₂+𝐺₁𝐺_𝑧𝐺_𝑥𝐶₁+𝐺₁𝐺_𝑧𝐺_𝑥𝐶₂+2𝐺₂𝐺_𝑧𝐺₂+𝐺_𝑥𝐶₂𝐺−𝛽²𝐺_𝑥𝐺₂+𝐺_𝑥𝐶₁+𝛽𝐺₁𝐺₂𝐺_𝑥𝐺₂+𝐺_𝑥+𝐺₁𝐺₂𝐺_𝑧𝐺₂+𝐺_𝑥=0, (11) where 𝐺_𝑥 and 𝐺_𝑧 represent the corresponding admittances of the parasitic resistances 𝑅_𝑥 and 𝑅_𝑧, respectively. The modified oscillation condition and oscillation frequency are 𝐺₂𝐺_𝑥(1+𝑘)𝐺₁𝐺₂+𝐺_𝑥=𝐶₁+𝐶₂𝐶₁−2𝑘𝐶₂𝜔^′_𝑜=𝐺₁𝐺₂𝐺_𝑥𝐶₁𝐶₂𝐺₂+𝐺_𝑥=𝐺_𝑥𝐺₂+𝐺_𝑥𝜔_𝑜. (12)(13) The parameter 𝑘 is defined as 𝐺𝑘=^𝑧𝛽𝐺_𝑥. (14)

Equations (12) and (13) reveal that the nonideal current tracking error 𝛽 and parasitic admittances 𝐺_𝑥 and 𝐺_𝑧 influence the oscillation condition and oscillation frequency. However, the influence of the parameter 𝑘 can be ignored because the parasitic admittance 𝐺_𝑥 is much larger than 𝐺_𝑧 in magnitude. Note also that the parasitic admittance 𝐺_𝑥 slightly changes the oscillation frequency on this circuit. This slight deviation can be compensated for by selecting 𝐺_𝑥≫𝐺₂ to minimize the influence on the circuit. Utilizing (13), the active and passive sensitivities of the circuit (Figure 4(a)) are 𝑆^𝜔′𝑜_𝐺1=𝑆^𝜔′𝑜_𝐺2=−𝑆^𝜔′𝑜_𝐶1=−𝑆^𝜔′𝑜_𝐶2=12,𝑆^𝜔′𝑜_𝐺𝑥=12𝐺₂𝐺₂+𝐺_𝑥,𝑆^𝜔′𝑜_𝛽=𝑆^𝜔′𝑜_𝐺𝑧=0. (15) For the condition 𝐺_𝑥≫𝐺₂, 𝑆^𝜔′𝑜_𝐺𝑥=0. The circuit exhibits a good sensitivity performance because all active and passive sensitivities are less than unity in magnitude. For Figure 4(b) circuit, the modified characteristic equation is 𝑆²𝐺1+^𝑧𝛽𝐺_𝑥𝐶₁𝐶₂+𝑆𝐺₁𝐶₁+𝐺₂𝐶₁+𝐺₃𝐶₁−𝐺₁𝐶₂+𝐺_𝑧𝛽𝐺_𝑥2𝐺₂𝐶₂+𝐺₁𝐶₁+𝐺₂𝐶₁+𝐺₃𝐶₁+𝐺₁𝐺₂+1𝛽𝐺₁𝐺₂𝐺_𝑧𝐺_𝑥+𝐺₂𝐺₃𝐺_𝑧𝐺_𝑥=0. (16) The modified oscillation condition and oscillation frequency are (1+𝑘)𝐺₁+𝐺₂+𝐺₃𝐺₁−2𝑘𝐺₂=𝐶₂𝐶₁𝜔^′_𝑜=𝐺₂𝐺₁+𝑘𝐺₃/(1+𝑘)𝐶₁𝐶₂=𝜔_𝑜+𝑘𝐺1+𝑘²𝐺₃𝐶₁𝐶₂. (17)(18)

Equations (17) and (18) show that the parameter 𝑘 slightly changes the oscillation condition and oscillation frequency, respectively. Again, this slight deviation can be overlooked because the parameter 𝑘 represents a very small value on the proposed circuits. The active and passive sensitivities for this circuit are determined in (19). Equation (19) shows that the active and passive sensitivities are all low because the parameter 𝑘 is nearly zero: 𝑆^𝜔′𝑜_𝐺2=−𝑆^𝜔′𝑜_𝐶1=−𝑆^𝜔′𝑜_𝐶2=12,𝑆^𝜔′𝑜_𝐺𝑧=−𝑆^𝜔′𝑜_𝛽=12𝑘𝐺₃(1+𝑘)²𝐺₁+𝑘(1+𝑘)𝐺₃,𝑆^𝜔′𝑜_𝐺𝑥1=−2𝑘𝐺₃/(1+𝑘)(1+𝑘)𝐺₁+𝑘𝐺₃,𝑆^𝜔′𝑜_𝐺1=121+𝑘𝑘1+𝐺₃,𝑆+1_{𝜔′𝑜𝐺3}=12𝑘𝐺₃(1+𝑘)𝐺₁+𝑘𝐺₃. (19) The circuit depicted in Figure 4(c) has the following modified characteristic equation: 𝑆²𝐺1+^𝑧𝛽𝐺_𝑥𝐶₂+𝐶₃𝐶₁+𝑆𝐺₁𝐶₁+𝐺₂𝐶₁−𝐺₁𝐶₂+𝐺_𝑧𝛽𝐺_𝑥𝐺₂𝐶₃+2𝐺₂𝐶₂+𝐺₁𝐶₁+𝐺₂𝐶₁+𝐺₁𝐺₂−1𝛽𝐺₁𝐺₂𝐺_𝑧𝐺_𝑥=0. (20) The modified oscillation condition and oscillation frequency are ()𝐺1+𝑘1+²𝐺₁+𝑘𝐺₂𝐶₃𝐺₁𝐶₁=𝐶₂𝐶₁,𝜔^′_𝑜=(1−𝑘)𝐺₁𝐺₂(1+𝑘)𝐶₁𝐶₂+𝐶₃=1−𝑘𝜔1+𝑘^𝑜. (21)(22)

Equations (21) and (22) show that the parameter 𝑘 affects the oscillation condition and oscillation frequency, respectively. However, the influence of the nonideal effect can be nearly disregarded because the parameter 𝑘 is a very small value that ideally approaches zero. The active and passive sensitivities of the circuit are 𝑆^𝜔′𝑜_𝐺1=𝑆^𝜔′𝑜_𝐺2=−𝑆^𝜔′𝑜_𝐶1=12,𝑆^𝜔′𝑜_𝐺𝑥=−𝑆^𝜔′𝑜_𝐺𝑧=𝑆^𝜔′𝑜_𝛽=𝐺_𝑧1−𝑘²,𝑆^𝜔′𝑜_𝐶21=−2𝐶₂𝐶₂+𝐶₃,𝑆^𝜔′𝑜_𝐶31=−2𝐶₃𝐶₂+𝐶₃. (23)

Equation (23) shows that when 𝐶₃>𝐶₂ is set, the values of 𝑆^𝜔′𝑜_𝐶2 and 𝑆^𝜔′𝑜_𝐶3do not exceed 50%. In addition,𝑆^𝜔′𝑜_𝐺𝑥,𝑆^𝜔′𝑜_𝐺𝑧, and𝑆^𝜔′𝑜_𝛽 approach zero because the admittance 𝐺_𝑧 is a very small value (𝐺_𝑧=0, in ideal case). Thus, the active and passive sensitivities are all low. Thus, to eliminate the nonideality effects and reduce the influence of sensitivity on the proposed circuits, the following conditions should be met: 𝐺_𝑥≫𝐺_𝑧, 𝐺_𝑥≫𝐺₂, and 𝐶₃>𝐶₂. In considering the integration aspects, the proposed oscillator circuits with the top plate and bottom plate parasitic capacitances of 𝐶₁ and 𝐶₂ may render to alter the order of the oscillator circuits and change its oscillation frequency. To reduce the influences of the top plate and bottom plate parasitic capacitances of 𝐶₁ and 𝐶₂ on the proposed oscillators, an advanced layout technology can be applied to overcome this obstacle [31]. Table 2 summarizes the key equations for the proposed oscillators.

Table 2 

Key equations for the proposed oscillators.

The frequency stability is an important performance criterion for sinusoidal oscillators [1]. The frequency stability factor 𝑆_𝐹 is defined as 𝑆_𝐹=𝑑Φ𝜇𝑑𝜇_𝜇=1, (24) where 𝜇=𝜔/𝜔₀ and Φ(𝜇) represents the phase function of the open loop transfer function for the oscillator circuit. Using the definition expressed in (24), Table 2 gives the frequency stability factor for the proposed oscillators. This table shows that good frequency stability can be obtained by choosing a larger value of 𝑛 for the proposed circuits.

4. Simulation and Experimental Results

To verify the feasibility of the proposed circuits, commercial AD844AN ICs were adopted to implement an OTRA (Figure 3) to execute the experimental tests. All experiments were performed at a supply voltage of ±5 V. The proposed circuits were also simulated with circuit simulation program HSPICE using the CMOS OTRA implementation as shown in Figure 2. Feasible design procedures of the oscillation condition and the oscillation frequency for the proposed oscillators (Figure 4) were arranged as follows. For Figure 4(a) circuit, 𝐶₁=𝐶₂ was first assigned and an oscillation frequency was specified. Therefore, the values 𝑅₁ and 𝑅₂ can be determined using (4). For the Figure 4(b) circuit, 𝑅₁=𝑅₂ and 𝐶₂=𝑛𝐶₁ were chosen. From (6) and (7), 𝑅₃ can be determined when an oscillation frequency was assigned. For the final oscillator (Figure 4(c)), 𝐶₂=3𝐶₁ was first assigned and thus the ratio of 𝑅₁/𝑅₂ was decided from (9). Subsequently, the value of 𝐶₃ can be determined from (10) when an oscillation frequency was specified. For example, the oscillator in Figure 4(a) was designed with 𝑅₁=2.43 kΩ, 𝑅₂=1.1 kΩ, and 𝐶₁=𝐶₂=1 nF. Together with the nonideal parameters 𝛽=0.98, 𝑅_𝑥=50 Ω, and 𝑅_𝑧=3 MΩ, this resulted in 94.98 kHz theoretical oscillation frequency. The experimental results in Figure 6(a) show an oscillation frequency of 97.54 kHz, which is close to the theoretical prediction. The percentage error between theoretical and experimental result is 2.62%. Figure 6(b) displays the corresponding frequency spectrum. The percentage total harmonic distortion (THD) was measured as 2.52%. The experimental result shows the slight distortion on this circuit because Figure 4(a) circuit suggests a compact circuit topology with minimum RC design [9, 27, 28]. However, an additional auxiliary amplitude control circuit and technology can be used to yield a lower distortion of the generated output signal through external means [32]. The oscillator of Figure 4(b) was designed with 𝑅₁=𝑅₂=10.83 kΩ, 𝑅₃=29.6 kΩ, and 𝐶₁=0.1 nF, 𝐶₂=0.2 nF together with the nonideal parameters 𝛽=0.98, 𝑅_𝑥=50 Ω, and 𝑅_𝑧=3 MΩ. Figure 7 shows the experimental results of the output waveform and the corresponding frequency spectrum. In this case, the theoretical value of the oscillation frequency is 104.16 kHz, whereas experimental results (Figure 7(a)) reveal an oscillation frequency of 102.5 kHz. The percentage error between theoretical and experimental result is 1.59%. The percentage THD was measured as 2.64%.

(a)

(b)

Figure 6 

Experimental results for the circuit (Figure 4(a)): (a) output waveform and (b) corresponding frequency spectrum.

(a)

(b)

Figure 7 

Experimental results for the circuit (Figure 4(b)): (a) output waveform and (b) corresponding frequency spectrum.

The oscillator in Figure 4(c) was designed with 𝑅₁=2 kΩ, 𝑅₂=1 kΩ, and 𝐶₁=0.1 nF, 𝐶₂=0.3 nF, 𝐶₃=12.4 nF. The theoretical value of the oscillation frequency was determined as 99.85 kHz. The experimental results in Figure 8(a) reveal an oscillation frequency of 101.3 kHz. The percentage error between theoretical and experimental result is 1.43%. Figure 8(b) indicates that the corresponding frequency spectrum and the percentage THD was measured as 2.98%.

(a)

(b)

Figure 8 

Experimental results for the circuit (Figure 4(c)): (a) output waveform and (b) corresponding frequency spectrum.

Considering the achievements in CMOS technology, Figure 2 presents an alternative implementation of OTRA for simulation testing. For this purpose, all of the proposed circuits in Figure 4 were simulated using the HSPICE program based on the CMOS OTRA (Figure 2). All simulations were performed by TSMC 0.35 μm MOS transistor parameters with the same aspect ratios as those in [15]. The CMOS OTRA (Figure 2) was biased with a power supply of ±2.5 V. The bias current and voltages 𝐼_𝐵=30 μA, 𝑉_𝑔1=−1 V, and 𝑉_𝑔2=1 V were set. Figure 9(a) shows the simulation results of the output waveform for Figure 4(a) with 𝑅₁=21.3 kΩ, 𝑅₂=9.85 kΩ, 𝐶₁=0.1 nF, and 𝐶₂=0.1 nF, where 𝑅₁ was designed to be larger than 𝑅₂ to achieve good frequency stability. Simulation results indicate that the oscillation frequency is 108.48 kHz (theoretical value is 109.87 kHz), yielding a percentage error of only 1.26% between the theoretical and simulation oscillation frequency results. These slight deviations in the oscillation frequency of the circuit from theoretical values were caused by the nonideality of the CMOS OTRA. Figure 9(b) shows that the simulation result of the frequency spectrum and the percentage THD was analyzed as 2.59%. The circuit in Figure 4(b) was simulated with the following values: 𝑅₁=12 kΩ, 𝑅₂=12 kΩ, 𝑅₃=12 kΩ, 𝐶₁=0.05 nF, and 𝐶₂=0.16 nF. Under these design values, the theoretical value of the oscillation frequency was calculated as 148.28 kHz. Figure 10 shows the simulation results of the output waveform and its output frequency spectrum. Figure 10(a) shows that the oscillation frequency of the output waveform is 150.01 kHz. Figure 10(b) shows that the percentage THD was analyzed as 2.71%, yielding a 1.15% percentage error between theoretical and simulation result of the oscillation frequency.

(a)

(b)

Figure 9 

Simulation results for the circuit (Figure 4(a)) using CMOS OTRA (Figure 2): (a) output waveform and (b) corresponding frequency spectrum.

(a)

(b)

Figure 10 

Simulation results for the circuit (Figure 4(b)) using CMOS OTRA (Figure 2): (a) output waveform and (b) corresponding frequency spectrum.

For the circuit in Figure 4(c), the passive components were chosen as 𝑅₁=20 kΩ, 𝑅₂=9 kΩ, 𝐶₁=0.05 nF, 𝐶₂=0.15 nF, and 𝐶₃=0.1 nF. This design yields a theoretical oscillator frequency of 106.1 kHz. Figure 11(a) shows the output waveform view obtained from HSPICE simulation for the chosen example. Simulation results show an oscillation frequency of 105.08 kHz, which is close to the theoretical prediction. The percentage error of the oscillation frequency between theoretical and simulation result is 0.96%. Figure 11(b) displays the corresponding output frequency spectrum, with the percentage THD analyzed as 0.56%. Once again, these results verify that the HSPICE simulations are in good agreement with the theoretical analysis. Simulation results show that the CMOS OTRA-based solutions provide the better output waveforms with low signal distortion. With regard to thehighest applicable operating frequency of the proposed circuit (Figure 4(c)), an experimental test with values 𝑅₁=15 kΩ, 𝑅₂=7.5 kΩ, 𝐶₁=0.03 nF, 𝐶₂=0.1 nF, and 𝐶₃=0.01 nF was executed to explore this characteristic. Figure 12 shows the simulation result for the output waveform of the circuit (Figure 4(c)) with an oscillation frequency of 260.35 kHz, which is close to the theoretical value of 261.21 kHz. The highest applicable operating frequency of the proposed oscillator was only demonstrated at approximated several hundreds of kHz based on the CMOS OTRA circuit (Figure 2). In this case, the percentage error between theoretical and experimental result is 0.79%. To demonstrate the properties used to control oscillation frequency by using resistors, Figure 4(b) circuit is employed to investigate such phenomenon. By adopting 𝐶₁=0.05 nF and 𝐶₂=0.16 nF, 𝑅₁=𝑅₂=𝑅₃=𝑅 was assigned and varied from 10 kΩ to 20 kΩ in 1 kΩ steps. Figure 13 shows the theoretical and simulation results for the variation of the oscillation frequency. The experimental results correspond with the theoretical prediction. Experimental tests suggest that the proposed oscillators can be implemented using commercially available AD844AN ICs or CMOS technology.

(a)

(b)

Figure 11 

Simulation results for the circuit (Figure 4(c)) using CMOS OTRA (Figure 2): (a) output waveform and (b) corresponding frequency spectrum.

Figure 12 

Simulation result of the highest applicable oscillation of the circuit (Figure 4(c)).

Figure 13 

Variation of the oscillation frequency against 𝑅 for the circuit (Figure 4(b)).

5. Conclusions

This study reports three new sinusoidal oscillators that have not been seen in the open literature. Each circuit consists of a single OTRA with a few external passive components. The first circuit features the least RC components design. The second and third circuits provide independent control of the oscillation condition and oscillation frequency, respectively. The proposed circuits also exhibit low active and passive sensitivities to oscillation frequency, and most parasitic parameters in the proposed circuits disappear due to the OTRA’s internal ground input terminals. The HSPICE simulations and experiment measurements in this study verify the effectiveness of the proposed circuits. The proposed topologies provide brand-new sinusoidal oscillators for OTRA devices. Because of their simplicity, these new schemes can be expected to find wide applications in modern analog circuit systems.

Conflict of Interests

The author declares that there is no conflict of interests regarding the publication of this paper.