Research Article | Open Access
A Novel Inverter Topology for Single-Phase Transformerless PV System
Transformerless photovoltaic (PV) power system is very promising due to its low cost, small size, and high efficiency. One of its most important issues is how to prevent the common mode leakage current. In order to solve the problem, a new inverter is proposed in this paper. The system common mode model is established, and the four operation modes of the inverter are analyzed. It reveals that the common mode voltage can be kept constant, and consequently the leakage current can be suppressed. Finally, the experimental tests are conducted. The experimental results verify the effectiveness of the proposed solution.
The transformerless PV inverter has the prominent advantages of the small size, low cost, and high efficiency . And more and more commercial transformerless PV inverters have been developed in recent years. However, there is no galvanic isolation between the input and output sides of the transformerless inverter, so it is prone to common mode leakage current problems . The common mode leakage current not only affects the electromagnetic compatibility of the inverter , but also leads to the potential human safety problems .
In order to solve this problem, Sunways Company developed HERIC inverter . SMA Company developed H5 inverter . Xiao and Xie presented a leakage current analytical model  and then developed the new optimized H5 , and split-inductor neutral point clamped inverters . Cavalcanti et al. developed the space vector modulation techniques for three-phase two-level  and three-level  inverters. Guo et al. developed the carrier modulation techniques for three-phase inverters . Yang et al. , Zhang et al. , and San et al.  developed the improved H6 inverter. And there is an increasing attention to develop the new inverter for transformerless PV applications.
The main contribution of this paper is to develop a new single-phase transformerless PV inverter. Compared with HERIC in , only one auxiliary switch and gating driver are needed in the proposal. While in HERIC, two auxiliary switches are needed. Also, two auxiliary gating drivers should be designed for two auxiliary switches. Therefore, the proposal is more cost-effective and reliable, due to less auxiliary switches and gating drivers are used. On the other hand, three semiconductors conduct current during modes 2 and 4. While in Heric, two semiconductors conducts current during modes 2 and 4. Therefore, the main difference is that one additional diode loss. With the development of the commercially available Sic diode, the diode loss will be very small. So this difference due to one additional diode loss would be small. Finally, the theoretical analysis and experimental results validate the proposed solution.
2. Proposed Topology
Figure 1 illustrates the schematic diagram of the proposed single-phase inverter. It consists of five switches and four diodes. is the parasitic capacitance between PV array and ground. The capacitance value depends on many conditions such as the PV panel frame structure, weather conditions, and humidity, and it is generally up to 50–150 nF/kW. is the grid voltage, and is the dc bus voltage. and are filter inductors, respectively.
The common mode voltage and differential mode voltage are defined as
From (1), the following voltage equations can be obtained:
Figure 2 shows the system common mode model. It can be observed that the differential mode voltage has the effect on the system common mode current if . Therefore, the filter inductance of should be designed the same value as that of ; that is, . So the differential mode voltage will not contribute the common mode current, as shown in Figure 2 . Note that the common mode current is mainly due to the high frequency switching components. Therefore, the effect of grid voltage on the common mode voltage is neglected, because its frequency is much lower than the switching frequency .
On the other hand, from Figure 2, it can be observed that the common mode leakage current will be eliminated on condition that the common mode voltage can be kept constant all the time. The reason is that the common mode leakage current, which passes through , depends on . When the common mode voltage is constant, the voltage across is constant as well. That is . Therefore, the common mode leakage current can be eliminated if the common mode voltage is constant. In order to achieve this goal, the following will present the operation principle.
In Mode 1, the switches and turn on, and other switches turn off. The differential mode voltage is equal to the dc bus voltage of , while the common mode voltage can be expressed as
In Mode 2, only the switch turns on, and other switches turn off. The current flows through and diodes. In this case, the differential mode voltage is 0, while the common mode voltage remains unchanged as
In Mode 3, the switches and turn on, and other switches turn off. The differential mode voltage is , while the common mode voltage can be expressed as
In Mode 4, only the switch turns on, and other switches turn off. The current flows through and diodes. In this case, the differential mode voltage is 0, while the common mode voltage remains unchanged as
From the above theoretical analysis, it can be observed that the common mode voltage remains constant during the whole operation cycle. Consequently, the common mode leakage current can be significantly suppressed, according to theoretical analysis of Figure 2.
The system design in terms of passive and active components is presented as follows. The rated system power is 1.5 kW, dc bus voltage is 400 V, grid voltage is 220 Vac, grid frequency is 50 Hz, and inverter switching frequency is 10 kHz.
First of all, the active components such as the switches are designed in terms of the operating voltage, on-state current. The rated voltage and current stresses of switches (, , , , ) and diodes are 400 V and 10 A, respectively. Therefore, the IRG4IBC30S IGBT from International Rectifier is selected for five switches (, , , , ). Its collector-to-emitter breakdown voltage is 600 V, and the continuous collector currents are 23.5 A and 13 A, respectively, in case of °C and °C. The diode is FR20J02GN-ND from GeneSiC Semiconductor.
Another design consideration is the filter inductor. Its inductance can be calculated according to the commonly used design criterion, in which the maximum current ripple magnitude is less than 10% of the rated current. The filter inductor current ripple can be calculated from Figure 4 as follows.
(a) Mode 1
(b) Mode 2
(c) Mode 3
(d) Mode 4
In mode 1, the inductor current increases:where and is the amplitude and angular frequency of the grid voltage and is the time interval of mode 1.
In mode 2, the inductor current decreases:where is the time interval of mode 2, , and is the switching cycle.
In steady state, . So . Considering , we can obtain
The current ripple reaches its maximum value when . In this case, the maximum current ripple is
In this paper, is 400 V, is 100 us, the rated current is 10 A, and the maximum current ripple should be less than 1 A; therefore, the filter inductor should be designed as follows:
3. Simulation and Experimental Results
In order to further verify the effectiveness of the proposed inverter, the performance test is conducted in MATLAB/Simulink. The components and parameters are listed as follows: system rated power is 1.5 kW, dc bus voltage is 400 V, grid voltage is 220 Vac, grid frequency is 50 Hz, switching frequency is 10 kHz, filter inductor is mH, and parasitic capacitor is = 150 nF. The leakage current is obtained by measuring the current through the parasitic capacitor .
Figure 5 shows the operation of the proposed converter. The simulation results of the operation mode 1 and mode 2 are shown in Figure 5(a). In agreement with the theoretical analysis in Figure 4(a), when the switches and turn on, the collector-to-emitter voltage of is approximately zero, and its current increases with a slope of . The simulation result waveforms of are the same as those of in mode 1 and thus not duplicated here for simplicity.
(a) Operation mode 1 and mode 2
(b) Operation mode 3 and mode 4
In mode 2, only the switch turns on, the collector-to-emitter voltage of changes from 400 V (in mode 1) to zero (in mode 2), and its current decreases with a slope of .
The last figure in Figure 5(a) shows the filter inductor current, it can be observed that the inductor current charges (in mode 1) and discharges (in mode 2) during a switching cycle, and the current ripple is less than 1 A, which is in good agreement with the design consideration in Section 2.
The simulation results of the operation mode 3 and mode 4 are shown in Figure 5(b). In agreement with the theoretical analysis in Figure 4(c), when the switches and turn on, the collector-to-emitter voltage of is approximately zero, and its current increases in mode 3. In mode 4, only the switch turns on, the collector-to-emitter voltage of changes from 400 V (in mode 3) to zero (in mode 4), and its current decreases. The last figure in Figure 5(a) shows the filter inductor current, it can be observed that the inductor current charges and discharges during a switching cycle, and the current ripple is less than 1 A, which is in good agreement with the design consideration in Section 2.
Figure 6 shows the simulation results of output waveforms in the time and frequency domains. It can be observed that the output grid current is sinusoidal, and its total harmonic distortion (THD) is well below 5%, as specified in IEEE Std. 929-2000.
The simulation results of the common mode voltage and leakage current are shown in Figure 7. It can be observed that the common mode voltage is constant, which is in agreement with the theoretical analysis in Section 2. On the other hand, the parasitic capacitor voltage does not include any high frequency common mode voltage, and therefore the leakage current is significantly reduced, as shown in Figure 7(c). Its peak value is below 300 mA, and the RMS value is below 30 mA, which meets the international standard VDE 0126-1-1.
(a) Common mode voltage
(b) Parasitic capacitor voltage
(c) Common mode leakage current and spectrum
As shown in Figure 8, with the proposed topology, it can be observed that the parasitic capacitor voltage has only the fundamental frequency component, without any high frequency components. Therefore, the leakage current can be effectively reduced below 300 mA, which complies with the international standard VDE 0126-1-1.
This paper has presented the theoretical analysis and experimental verification of a new inverter for transformerless PV systems. The proposed inverter has the following interesting features. It can keep the system common mode voltage constant during the entire operation cycle. Consequently, the common mode leakage current can be significantly reduced well below 300 mA, which meets the international standard VDE 0126-1-1. Therefore, it is attractive and a promising alternative topology for transformerless PV system applications.
Conflict of Interests
The author declares that there is no conflict of interests regarding publication of this paper.
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Copyright © 2016 Haiyan Cao. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.