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Active and Passive Electronic Components
Volume 2016, Article ID 4517292, 8 pages
Research Article

Bus Implementation Using New Low Power PFSCL Tristate Buffers

1Department of Electronics and Communication Engineering, Delhi Technological University, Delhi 110042, India
2Department of Electronics and Communication Engineering, Bharati Vidyapeeth’s College of Engineering, Delhi 110063, India
3Department of EEE/E&I, Birla Institute of Technology, Pilani University, K. K. Birla Goa Campus, Goa 403726, India

Received 30 November 2015; Accepted 24 January 2016

Academic Editor: Stephan Gift

Copyright © 2016 Neeta Pandey et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper proposes new positive feedback source coupled logic (PFSCL) tristate buffers suited to bus applications. The proposed buffers use switch to attain high impedance state and modify the load or the current source section. An interesting consequence of this is overall reduction in the power consumption. The proposed tristate buffers consume half the power compared to the available switch based counterpart. The issues with available PFSCL tristate buffers based bus implementation are identified and benefits of employing the proposed tristate buffer topologies are put forward. SPICE simulation results using TSMC 180 nm CMOS technology parameters are included to support the theoretical formulations. The performance of proposed tristate buffer topologies is examined on the basis of propagation delay, output enable time, and power consumption. It is found that one of the proposed tristate buffer topology outperforms the others in terms of all the performance parameters. An examination of behavior of available and the proposed PFSCL tristate buffer topologies under parameter variations and mismatch shows a maximum variation of 14%.