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Active and Passive Electronic Components
Volume 2017 (2017), Article ID 1609787, 12 pages
https://doi.org/10.1155/2017/1609787
Research Article

A Novel Floating Memristor Emulator with Minimal Components

1College of Information Engineering, Xiangtan University, Xiangtan, Hunan 411105, China
2Department of Optoelectronic Engineering, Xiangtan University, Xiangtan, Hunan 411105, China

Correspondence should be addressed to Zhijun Li

Received 4 July 2017; Revised 23 August 2017; Accepted 6 September 2017; Published 19 October 2017

Academic Editor: Jiun-Wei Horng

Copyright © 2017 Zhijun Li et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A new floating emulator for the flux-controlled memristor is introduced in this paper. The proposed emulator circuit is very simple and consists of only two current feedback operational amplifiers (CFOAs), two analog multipliers, three resistors, and two capacitors. The emulator can be configured as an incremental or decremental type memristor by using an additional switch. The mathematical model of the emulator is derived to characterize its behavior. The hysteresis behavior of the emulator is discussed in detail, showing that the pinched hysteresis loops in - plane depend not only on the amplitude-to-frequency ratio of the exciting signal but also on the time constant of the emulator circuit itself. Experimental tests are provided to validate the emulator’s workability.

1. Introduction

The memristor, next to the resistor, the capacitor, and the inductor, was postulated as the fourth passive circuit element by Chua in 1971 [1]. It is defined as a two-terminal element that provides the missing constitutive relationship between charge and flux. Ignited by the successful fabrication of a real nanoscale memristor by HP Labs in 2008 [2], tremendous research has been devoted to explore memristor-based potential applications in such areas as resistive random access memory (RRAM) [3, 4], analog circuits [5, 6], digital circuits [7, 8], chaotic circuits [9, 10], and neural networks [11, 12]. Although memristor has many potential applications, it is not available as a universal electronic device for ordinary researchers. For this reason, a lot of SPICE models [1315] were implemented to serve as a possible alternative to simulate memristor. But they cannot be used to build real-world applications. Recently, Bio Inspired Technologies has launched the world’s first commercially available memristor [16]. However, it has a high price and can only be applied under special conditions in order to avoid irreparable damage [17]. Therefore, a replacement that behaves like a real memristor is still urgently needed to allow ordinary researchers to study memristor-based practical applications. Indeed, many memristor emulator circuits have been developed in recent years [1732]. For example, using a JFET to implement the required nonlinearity, a memristor emulator constructed with five operational amplifiers, a floating capacitor, a large number of resistors, and an analog multiplier is presented in [19]. In addition to its complexity, the emulator reported in [19] is grounded and therefore is unsuitable for use as a two-terminal device in more complicated circuits. A unified approach for transforming nonlinear resistors into memristors is developed in [20], but the resultant emulators based on this methodology are limited by grounded operation. Emulator presented in [21, 22] can well imitate the features of TiO2 memristor. However, the circuits are very complex and are built with an analog multiplier and a number of operational amplifiers (OAs), resistors, and MOS transistors. In order to make circuits in [21, 22] have a capacity of floating operation, further modification was made in [23] by adding a current conveyor. In [24], Sanchez-Lopez et al. proposed a floating memristor emulator which can operate at a high operating frequency (up to 14 kHz). But the circuit uses a large number of active and passive elements, namely, five CFOAs, one analog multiplier, and a number of passive elements. Two simplified emulators with higher operating frequency were presented in [17, 26]. However, the grounded restriction places a substantial obstacle on their connectivity with other circuit elements. The emulator circuit in [27] uses a light-dependent resistor (LDR) to provide the required nonlinearity. Although the emulator circuit is very simple, it can only work at low frequency and has a narrow variation range of memristance. Pershin and Ventra built a memristor emulator using digital and analog mixed circuits [28]. The resolution of its memristance, however, is limited by the limited performance of the A/D converters. Using diode-resistive networks to implement the required nonlinearity, a binary-level emulator was developed in [29] and a continuous-level emulator implemented by using the nonlinear transfer characteristics of OTA was presented in [30] by Abuelma’atti and Khalifa. However, the grounded restriction is still the main obstacle to its connectivity with other circuit elements. A floating emulator, which is built with four CFOAs and avoids the use of analog multipliers, was developed by the same authors [31]. In order to make it successfully emulate a floating memristor, the emulator circuit must satisfy strict parameter matching conditions. An electronically tunable memristor emulator circuit is presented in [32] and its memristance value can be controlled by changing transconductance parameters of the used OTAs.

In this paper, we propose a floating memristor emulator, which is built with two CFOAs, two analog multipliers, and five passive elements. In fact, multipliers are often used to realize the product of voltage and flux (current and charge) for the design of the flux-controlled (charge-controlled) memristor emulators [2127]. Different from the above design methods, however, herein the multipliers are employed to construct a floating voltage-controlled resistor (VCR). The emulator is implemented by using the flux across it as the controlled voltage of the VCR. The proposed emulator not only has a simple topology but also can be configured as an incremental or decremental type memristor. The mathematical model of the emulator is derived in detail. Its hysteresis behavior is further discussed, showing that the pinched hysteresis loops in - plane depend not only on the amplitude-to-frequency ratio of the exciting signal but also on the time constant of the emulator circuit itself. Furthermore, PSpice simulations and experimental tests are included to demonstrate the properties of the emulator. The organization of the paper is as follows: in Section 2, we introduce our emulator circuit and derive its mathematical model, hysteresis behavior analysis is performed in Section 3, and PSpice simulations and experimental results are given in Sections 4 and 5, respectively. We conclude the paper in the last section.

2. Proposed Floating Emulator Circuit

The memristor completes the missing link between charge and flux . When its constitutive relation is expressed as a single-valued function , the memristor is flux-controlled and can be characterized by its memductance , which describes the ratio of change of the charge with respect to the flux across the device:The corresponding - relationship of the memristor in this case is expressed as

The proposed floating flux-controlled memristor emulator circuit is shown in Figure 1. It is composed of two AD844 type CFOAs, two AD633 type analog multipliers, three resistors, and two capacitors. Here, and are parasitic resistors at -terminal of and ; and and and are the parasitic resistors and capacitors associated with -terminal. Each CFOA is characterized by the following terminal relations [20]:where , , and are the port transfer ratios. From Figure 1, the current through the resistor can be expressed asThe current will be transferred to -terminal of and it will be integrated by the capacitors and to produce a output voltage at -terminal of given byThe influence of the parasitic resistor on the emulator circuit is negligible due to its high resistance value which is approximately 3 M. Substituting (4) into (5), one can obtain the output voltage given byConsidering the fact that , (6) can be rewritten aswhere corresponds to the flux across the emulator and it is defined as . Here, we consider that the initial condition of the integrator is zero. Similarly, one can obtain the output voltage :Analog multipliers and and the resistors and construct a floating voltage-controlled resistor (VCR) and is the controlled voltage. Referring to the input-to-output characteristic of AD633, the output voltages and can be given asThus, the currents and can be expressed asIt is can be inferred from (10) that holds if is satisfied. Thus, the equivalent conductance of the VCR can be described aswhere . From Figure 1, when the switch is switched to node , that is, , the emulator realizes an incremental type memristor and the corresponding memductance can be expressed asWhen the switch is switched to node , that is, , the emulator is equivalent to a decremental type memristor whose memductance is decided byThus the emulator has the same advantage as the emulators in [17, 23]; that is, the incremental or decremental type memristor can be interchanged by using an additional switch . Due to , , , and and assuming that , (12) and (13) can be described as the following unified expression:It can be seen from (14) that the two different type memductances are linearly dependent on the flux ; thus the emulator is flux-controlled, and it can be controlled by a voltage imposed on the input terminals.

Figure 1: The proposed floating memristor emulator circuit.

3. Hysteresis Behavior Analysis

In order to study the hysteresis behavior of the proposed emulator, assuming that a sinusoidal voltage is applied on terminals and , the flux across the device is . Note that the initial condition of the integrator, for the sake of simplicity, is considered as zero. As a consequence, the memductance can be calculated asIt is seen from (15) that the memductance is composed of a linear time-invariant conductance and a linear time-varying conductance. The pinched hysteresis behavior of the emulator is dependent on the relationship between the time-varying and time-invariant parts of the memductance [21]. The relationship between the two parts can be described by the ratio of their amplitudes, given aswhere is the time constant of the emulator itself; is the amplitude-to-frequency ratio of the stimulating signal. From (16), one can deduce that the pinched hysteresis behavior depends not only on the amplitude-to-frequency ratio of the stimulating signal but also on the time constant of the emulator circuit itself. There are three cases between and the pinched hysteresis loop of the proposed memristor:(1) when . The memductance is dominated by a linear time-invariant conductance and the pinched hysteresis loop shrinks into a straight line.(2) when . The corresponding memductance variation range is from (15) and the maximum pinched hysteresis loop can be achieved.(3) when . The memductance has zero or negative conductance value and the hysteresis loop is lost.As a consequence, in order to hold the pinched hysteresis loop, the numerical value of must lie on the interval . This means that must be updated according to and . The task can be done by updating the values of capacitors and with the following expression:For simplicity, we assume that , ,  Ω, and ; the circuit parameters of the chosen elements in Figure 1 for different operating frequency are given in Table 1. It is worth noting that the parasitic capacitors and are negligible, since their values are far less than those of the capacitors and .

Table 1: Circuit parameters for different frequency ranges.

4. PSpice Simulations

In order to verify the workability of the proposed emulator, using the circuit parameters given in Table 1 for  nF, the circuit was simulated by PSpice simulator. A sinusoidal voltage with  Hz and is applied across the memristor; the transient waveforms of , , and in the incremental type emulator are shown in Figure 2(a). The corresponding hysteresis loop is pinched at the origin in - plane, as illustrated in Figure 2(b). It can be seen from Figure 2(a) that the injected sinusoidal voltage produces a distorted current due to the nonlinearity of the memductance. Inspection of Figure 2(a) clearly also shows that the memductance varies periodically in the range of 0 to 200 uS under the sinusoidal voltage excitation. The similar simulation results, as shown in Figure 3, are obtained with the same circuit parameters when the circuit is configured as the decremental type memristor. Comparing Figure 2(b) with Figure 3(b), one can find that the incremental type memristor and the decremental type memristor have the same hysteresis loop in - plane. But the hysteresis loop of the incremental type memristor moves counterclockwise in the first quadrant and clockwise in the third quadrant, while that of the decremental type memristor is just the reverse.

Figure 2: PSpice simulation results obtained with the incremental type memristor. (a) Time waveforms of the input voltage , the input current , and the memductance W; (b) hysteresis loops in - plane operating at 10 Hz.
Figure 3: PSpice simulation results obtained with the decremental type memristor. (a) Time waveforms of the input voltage , the input current , and the memductance W; (b) hysteresis loops in - plane operating at 10 Hz.

In order to observe the impact of circuit parameter variations on the pinched hysteresis loop, Monte Carlo analysis was performed for all passive elements with the above circuit parameters, where 5% Gaussian deviations were used. As a consequence, Figures 4(a) and 4(b) illustrate the simulation results for the incremental and the decremental types, respectively. As seen from Monte Carlo analysis results, the proposed emulator circuit has reasonable sensitivity performances.

Figure 4: Monte Carlo analysis of the emulator for all passive elements: (a) the incremental type and (b) the decremental type.

5. Experimental Tests

The emulator circuit was also implemented with off-the-shelf electronic devices on a prototype PCB for experimental validation and observation of the hysteresis behavior. Circuit parameters for different operating frequency ranges used in experimental tests are presented in Table 1. Since the voltage is proportional to the current with coefficient from Figure 1, is used to indirectly represent the current in the process of experimental tests. In order to obtain the voltage , an additional differential amplifier circuit built with operational amplifiers is also included in the experimental testing platform, as shown in Figure 5.

Figure 5: Experimental testing platform.

When a sinusoidal voltage signal with  Hz and is applied to the emulator circuit, the transient waveforms of and are shown in Figure 6(a). The hysteresis loop is pinched at the origin in - plane as shown in Figure 6(b). When the stimulus frequency is increased to 50 Hz and 100 Hz, the corresponding hysteresis loops are illustrated in Figures 6(c) and 6(d), respectively. Inspection of Figures 6(b)6(d) clearly shows that the lobe area decreases gradually as the frequency increases, and when is increased to 100 Hz the hysteresis loop shrinks into a straight line. On the contrary, when the stimulus frequency is decreased to 7 Hz, which results in from (16), the hysteresis loop shown in Figure 6(e) is not complete and it is in a state of imminent disappearance. Figures 6(b)6(e) demonstrate the unique property of memristors, namely, the frequency-dependence of hysteresis loop.

Figure 6: Experimental results of the incremental type emulator when  nF. (a) waveforms of the input voltage and input current in the time domain; (b), (c), (d), and (e) represent hysteresis loops in - plane operating at 10 Hz, 50 Hz, 100 Hz, and 7 Hz, respectively. The time scale is 40 ms/div, and scales are 0.2 V/div for -axis and 0.2 V/div for -axis.

Furthermore, in order to maintain the hysteresis loop at high frequency, we scale down the capacitors and to 10 nF. Figures 7(a) and 7(b) show the experimental results for  Hz and  Hz, respectively. When stimulus frequency is increased to 1 kHz, the memductance is mainly dominated by the linear time-invariant conductance and the corresponding hysteresis loop approximates a straight line as shown in Figure 7(c).

Figure 7: Experimental results of the incremental type emulator when  nF. (a), (b), and (c) represent hysteresis loops in - plane operating at 100 Hz, 500 Hz, and 1 kHz, respectively. The scales are 0.2 V/div for -axis and 0.2 V/div for -axis.

Similarly, when the capacitors and are scaled down to 1 nF, the pinched hysteresis loops operating at = 1 kHz,  kHz, and = 10 kHz are given in Figures 8(a), 8(b), and 8(c), respectively. When the capacitors and are further scaled down to 100 pF, the emulator circuit can still perform hysteresis behavior at  kHz as shown in Figure 9(a). Unfortunately, when the stimulus frequency is increased to 35 kHz, the hysteresis loop does not pinch at the origin and thus performs an asymmetrical behavior as shown in Figure 9(b). This deformation will become more and more serious with the increase of the stimulus frequency. Figure 9(c) illustrates the hysteresis loop operating at 50 kHz. As can be observed, not only is the pinched hysteresis loop more deviated from the origin, but also the areas enclosed in the first and third quadrants are not equal.

Figure 8: Experimental results of the incremental type emulator when  nF. (a), (b), and (c) represent hysteresis loops in - plane operating at 1 kHz, 5 kHz, and 10 kHz, respectively. The scales are 0.2 V/div for -axis and 0.2 V/div for -axis.
Figure 9: Experimental results of the incremental type emulator when  pF. (a), (b), and (c) represent hysteresis loops in - plane operating at 10 kHz, 35 kHz, and 50 kHz, respectively. The scales are 0.2 V/div for -axis and 0.2 V/div for -axis.

The same experimental tests were conducted on the decremental type emulator. The pinched hysteresis loops can also be obtained by updating the capacitors and for different operating frequency ranges. For example, Figures 10(a), 10(b), and 10(c) illustrate the hysteresis loops operating at 1 kHz, 5 kHz, and 10 kHz, respectively. When the capacitors and are scaled down to 100 pF, the hysteresis loops operating at 10 kHz, 35 kHz, and 50 kHz are depicted in Figures 11(a), 11(b), and 11(c). It is evident from Figure 11(b) that the decremental emulator exhibits a deformed hysteresis loop just as the incremental emulator performs when the stimulus frequency is increased to the top limit of 35 kHz. This deformation is due mainly to the integrator circuit nonidealities, which is built with , , , and and along with the parasitic elements at their -terminals. The effect of the parasitic elements is negligible when the operating frequency is low. But when the operating frequency is increased monotonically, the parasitic elements manifest themselves as a high offset voltage imposed on the output of the integrator circuit. Due to this, the hysteresis loop does not pinch at the origin, and the areas enclosed in the first and third quadrants are not equal. In order to avoid the deformation of the hysteresis loop, both the incremental type and the decremental type memristors can only be used from 10 Hz to 35 kHz.

Figure 10: Experimental results of the decremental type emulator when  nF. (a), (b), and (c) represent hysteresis loops in - plane operating at 1 kHz, 5 kHz, and 10 kHz, respectively. The scales are 0.2 V/div for -axis and 0.2 V/div for -axis.
Figure 11: Experimental results of the decremental type emulator when  pF. (a), (b), and (c) represent hysteresis loops in - plane operating at 10 kHz, 35 kHz, and 50 kHz, respectively. The scales are 0.2 V/div for -axis and 0.2 V/div for -axis.

To further verify the effectiveness of the emulator, a pulse train (0.5 V, 10 ms duration, 30 ms period) is applied successively to the input of emulator circuit; the current is experimentally measured by using the circuit parameters given in Table 1 for  nF. Figures 12(a) and 12(b) illustrate the current responses of the incremental type and the decremental type memristors under successive voltage pulse excitation, respectively. For the incremental type, the current increases as more voltage pulses are applied. Thus, one can indirectly infer that its memductance increases as input voltage pulses are applied, whereas for the decremental type, we can derive the opposite conclusion.

Figure 12: Current responses of emulator under pulse excitation. (a) Incremental type emulator; (b) decremental type emulator. The time scale is 25 ms/div and scale is 0.2 V/div for -axis.

6. Conclusions

In this paper, a floating emulator circuit for the flux-controlled memristor has been presented. The proposed simulator is very simple and contains only two CFOAs, two multipliers, three resistors, and two capacitors. The emulator has been built with commercially available AD844 and AD633 ICs. Experimental results show that the proposed emulator circuit satisfies the three fingerprints of the memristor [30] and reveal how the frequency of the exciting voltage signal modifies its hysteresis behavior. When compared with the existing memristor emulator circuits, the proposed emulator not only has a simple topology but also can be configured as an incremental or decremental type memristor. Furthermore, the emulator can hold up the frequency-dependent pinched hysteresis loop at high frequency by updating the values of capacitors and . Detailed comparison of the presented emulator circuit with other published studies is summarized in Table 2. Since the emulator circuit can easily be implemented with the commercially available electronic devices, it can be used for memristor-based circuit designs and applications.

Table 2: Comparison of presented emulator with other published studies.

Conflicts of Interest

The authors declare that they have no conflicts of interest.

Acknowledgments

The authors would like to acknowledge the National Natural Science Foundation of China (Grants nos. 61176032 and 61471310) and the Natural Science Foundation of Hunan Province (Grants nos. 2015JJ2142 and 2015JJ2140) for supporting this research.

References

  1. L. O. Chua, “Memristor: the missing circuit element,” IEEE Transactions on Circuit Theory, vol. 18, no. 5, pp. 507–519, 1971. View at Publisher · View at Google Scholar
  2. D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, “The missing memristor found,” Nature, vol. 453, pp. 80–83, 2008. View at Publisher · View at Google Scholar · View at Scopus
  3. Y. C. Yang, F. Pan, Q. Liu, M. Liu, and F. Zeng, “Fully room-temperature-fabricated nonvolatile resistive memory for ultrafast and high-density memory application,” Nano Letters, vol. 9, no. 4, pp. 1636–1643, 2009. View at Publisher · View at Google Scholar · View at Scopus
  4. T. Nagata, M. Haemori, and Y. Yamashita, “Bias application hard X-ray photoelectron spectroscopy study of forming process of Cu/HfO2/Pt resistive random access memory structure,” Applied Physics Letters, vol. 99, no. 22, Article ID 223517, 2011. View at Google Scholar
  5. S. Shin, K. Kim, and S. M. Kang, “Memristor applications for programmable analog ICs,” IEEE Transactions on Nanotechnology, vol. 10, no. 2, pp. 266–274, 2011. View at Publisher · View at Google Scholar · View at Scopus
  6. S. Minaei, I. C. Göknar, M. Yıldız, and E. Yuce, “Memstor, memstance simulations via a versatile 4-port built with new adder and subtractor circuits,” International Journal of Electronics, vol. 102, no. 6, pp. 911–931, 2015. View at Publisher · View at Google Scholar · View at Scopus
  7. X. Zhu, X. J. Yang, C. Q. Wu, N. Xiao, J. J. Wu, and X. Yi, “Performing stateful logic on memristor memory,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 10, pp. 682–686, 2013. View at Publisher · View at Google Scholar · View at Scopus
  8. S. Shin, K. Kim, and S.-M. Kang, “Memristive XOR for resistive multiplier,” Electronics Letters, vol. 48, no. 2, pp. 78–80, 2012. View at Publisher · View at Google Scholar · View at Scopus
  9. A. Buscarino, L. Fortuna, M. Frasca, and L. V. Gambuzza, “A gallery of chaotic oscillators based on HP memristor,” International Journal of Bifurcation and Chaos, vol. 23, no. 5, Article ID 1330015, 14 pages, 2013. View at Publisher · View at Google Scholar · View at MathSciNet
  10. Z.-J. Li and Y.-C. Zeng, “A memristor oscillator based on a twin-T network,” Chinese Physics B, vol. 22, no. 4, Article ID 040502, 2013. View at Publisher · View at Google Scholar · View at Scopus
  11. H. Kim, M. P. Sah, C. Yang, T. Roska, and L. O. Chua, “Neural synaptic weighting with a pulse-based memristor circuit,” IEEE Transactions on Circuits and Systems. I. Regular Papers, vol. 59, no. 1, pp. 148–158, 2012. View at Publisher · View at Google Scholar · View at MathSciNet · View at Scopus
  12. Y. V. Pershin and M. Di Ventra, “Experimental demonstration of associative memory with memristive neural networks,” Neural Networks, vol. 23, no. 7, pp. 881–886, 2010. View at Publisher · View at Google Scholar · View at Scopus
  13. D. Batas and H. Fiedler, “A memristor SPICE implementation and a new approach for magnetic flux-controlled memristor modeling,” IEEE Transactions on Nanotechnology, vol. 10, no. 2, pp. 250–255, 2011. View at Publisher · View at Google Scholar · View at Scopus
  14. Y. V. Pershin and M. Di Ventra, “SPICE model of memristive devices with threshold,” Radioengineering, vol. 22, no. 2, pp. 485–489, 2013. View at Google Scholar · View at Scopus
  15. Z. Biolek, D. Biolek, and V. Biolková, “SPICE model of memristor with nonlinear dopant drift,” Radioengineering, vol. 18, no. 2, pp. 210–214, 2009. View at Google Scholar · View at Scopus
  16. http://www.bioinspired.net/.
  17. C. Sanchez-Lopez, M. A. Carrasco-Aguilar, and C. Muniz-Montero, “A 860 kHz grounded memristor emulator circuit,” International Journal of Electronics and Communications, vol. 73, pp. 23–33, 2017. View at Google Scholar
  18. D. Biolek, “Memristor emulators,” in Memristive Networks, A. Adamatzky, Ed., pp. 487–504, Springer, New York, NY, USA, 2014. View at Google Scholar
  19. J. Valsa, D. Biolek, and Z. Biolek, “An analogue model of the memristor,” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol. 24, no. 4, pp. 400–408, 2011. View at Publisher · View at Google Scholar · View at Scopus
  20. V. Biolkova, D. Biolek, and Z. Kolka, “Unified approach to synthesis of mutators employing operational transimpedance amplifiers for memristor emulation,” in Proceedings of the 11th International Conference on Instrumentation, Measurement, Circuits and Systems, pp. 110–115, 2012.
  21. H. Kim, M. P. Sah, C. Yang, S. Cho, and L. O. Chua, “Memristor emulator for memristor circuit applications,” IEEE Transactions on Circuits and Systems. I. Regular Papers, vol. 59, no. 10, pp. 2422–2431, 2012. View at Publisher · View at Google Scholar · View at MathSciNet · View at Scopus
  22. M. P. Sah, C. Yang, H. Kim, and L. O. Chua, “A voltage mode memristor bridge synaptic circuit with memristor emulators,” Sensors, vol. 12, no. 3, pp. 3587–3604, 2012. View at Publisher · View at Google Scholar · View at Scopus
  23. C. Yang, H. Choi, S. Park, M. P. Sah, H. Kim, and L. O. Chua, “A memristor emulator as a replacement of a real memristor,” Semiconductor Science and Technology, vol. 30, no. 1, Article ID 015007, 2015. View at Publisher · View at Google Scholar · View at Scopus
  24. C. Sanchez-Lopez, J. Mendoza-Lopez, M. A. Carrasco-Aguilar, and C. Muniz-Montero, “A floating analog memristor emulator circuit,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 5, pp. 309–313, 2014. View at Publisher · View at Google Scholar · View at Scopus
  25. C. Sanchez-Lopez, M. A. Carrasco-Aguilar, and F. E. Morales-López, “Offset reduction on memristor emulator circuits,” in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 1, pp. 296–299, December 2015. View at Publisher · View at Google Scholar · View at Scopus
  26. C. Sanchez-Lopez, M. A. Carrasco-Aguilar, and C. Muniz-Montero, “A 16 Hz–160 kHz memristor emulator circuit,” International Journal of Electronics and Communications, vol. 69, no. 9, pp. 1208–1219, 2015. View at Publisher · View at Google Scholar · View at Scopus
  27. X. Y. Wang, A. L. Fitch, H. H. C. Iu, V. Sreeram, and W. G. Qi, “Implementation of an analogue model of a memristor based on a light-dependent resistor,” Chinese Physics B, vol. 21, no. 10, Article ID 108501, 2012. View at Publisher · View at Google Scholar · View at Scopus
  28. Y. V. Pershin and M. Di Ventra, “Practical approach to programmable analog circuits with memristors,” IEEE Transactions on Circuits and Systems. I. Regular Papers, vol. 57, no. 8, pp. 1857–1864, 2010. View at Publisher · View at Google Scholar · View at MathSciNet · View at Scopus
  29. M. T. Abuelma'atti and Z. J. Khalifa, “A new memristor emulator and its application in digital modulation,” Analog Integrated Circuits and Signal Processing, vol. 80, no. 3, pp. 577–584, 2014. View at Publisher · View at Google Scholar · View at Scopus
  30. M. T. Abuelma'atti and Z. J. Khalifa, “A continuous-level memristor emulator and its application in a multivibrator circuit,” International Journal of Electronics and Communications, vol. 69, no. 4, pp. 771–775, 2015. View at Publisher · View at Google Scholar · View at Scopus
  31. M. T. Abuelma'atti and Z. J. Khalifa, “A new floating memristor emulator and its application in frequency-to-voltage conversion,” Analog Integrated Circuits and Signal Processing, vol. 86, no. 1, pp. 141–147, 2016. View at Publisher · View at Google Scholar · View at Scopus
  32. H. Sözen and U. Çam, “Electronically tunable memristor emulator circuit,” Analog Integrated Circuits and Signal Processing, vol. 89, no. 3, pp. 655–663, 2016. View at Publisher · View at Google Scholar · View at Scopus