Abstract
The total ionizing dose irradiation effects are investigated in Si vertical diffused MOSFETs (VDMOSs) with different gate dielectrics including single SiO2 layer and double Si3N4/SiO2 layer. Radiation-induced holes trapping is greater for single SiO2 layer than for double Si3N4/SiO2 layer. Dielectric oxidation temperature dependent TID effects are also studied. Holes trapping induced negative threshold voltage shift is smaller for SiO2 at lower oxidation temperature. Gate bias during irradiation leads to different shift for different gate dielectrics. Single SiO2 layer shows the worst negative at , while double Si3N4/SiO2 shows negative shift at , positive shift at , and negligible shift at .
1. Introduction
Silicon power MOSFET, especially vertical diffused MOSFET (VDMOS), is widely used for high power application due to its mature technology and cost efficiency. Nowadays, VDMOS is often used under harsh environment such as space, where it suffers from cosmic radiation [1–4]. To operate normally in space environment, Si VDMOSs must be able to withstand ionizing radiation such as total ionizing dose (TID). In this paper, we investigate TID effects in Si VDMOS with different gate dielectrics including single SiO2 layer and double Si3N4/SiO2 layer, different oxidation temperatures of SiO2, and different gate bias during irradiation.
2. Experiment Set-Up
The Si VDMOSs considered here are devices with well-known standard fabrication process except the gate dielectric deposition condition. Different silicon dioxide deposition conditions are carried out including different oxidation temperature from 800°C to 1000°C and with and without postoxidation annealing. In particular, double gate dielectric layer Si3N4/SiO2, having the same total thickness 50 nm (20 nm/30 nm) as that of single SiO2 layer, is fabricated to evaluate its hardness towards TID.
The irradiation test is performed with unpackaged devices wire-bonded on the test board under Co60 gamma source at a dose rate of 50 rad (Si)/s at room temperature, and the devices are remeasured after a total dose of 100 Krad is reached after 33 minutes. Irradiation was performed with different gate voltages () of 10 V, 0 V, and −5 V, with source terminal grounded and drain terminal of small voltage to guarantee a small current of about 100 mA for and drain terminal of 200 V (rated breakdown voltage). The bias-stress-only test is also performed without irradiation to account for the electrical stress influence, such as , . The bias-stress test is carried out by using the same biases ( of 10 V, 0 V, and −5 V) and time (33 minutes) comparable to those used in the irradiation experiments. Current-voltage characteristics are measured using Agilent 2902A parameter analyzer, and the measurements are carried out before and right after the irradiation/bias-stress.
3. Results and Discussion
Figure 1 shows versus characteristics of Si VDMOS with different gate dielectrics and different oxidation conditions before and after TID irradiation with during irradiation. Two types of gate dielectrics with the same total thickness of 50 nm are investigated including normal SiO2 layer (Figure 1(a)) and double Si3N4/SiO2 layer (Figure 1(b)), which is claimed to be more TID tolerant [5–9]. It can be observed that the threshold voltage shifts negatively for single SiO2 layer indicating a net holes’ trapping during positive-bias irradiation, and increases from 0.2 V to 0.71 with rising oxidation temperature from 800°C to 1000°C. The high temperature annealing (HTA) step after oxidation adds to the negative shift, suggesting a higher hole trapping ability. However, for double Si3N4/SiO2 layer, shifts positively at with a smaller than that of SiO2. It can be explained that, at positive-bias irradiation with , as shown in Figure 5(a), the irradiation created electrons in the SiO2 layer are swept to the Si3N4 and trapped there, forming net electrons trapping by compensating with the irradiation created holes in Si3N4 [10–12]. The number of electrons trapped in the Si3N4 is higher than the holes trapped in the SiO2, resulting in a net positive shift.
(a)
(b)
Figure 2 shows versus characteristics of Si VDMOS with different gate dielectrics and different oxidation conditions before and after TID irradiation with during irradiation. It can be observed that the devices with both single SiO2 dielectrics and double Si3N4/SiO2 dielectric (Figures 2(a) and 2(b)) have about the same value both before and after a total dose of 100 Krad (Si), indicating excellent gate control. The device with double Si3N4/SiO2 dielectric (Figure 2(b)) shows higher of 1.6 S compared to that of single SiO2 layer (1.3~1.4 S) at , which is due to a higher effective gate capacitance. The capacitance of Si3N4/SiO2 gate dielectric is measured to have a gate capacitance of 1.6 × 10−9 F, while SiO2 gate dielectric has a gate capacitance of 1.1 × 10−9 F due to a higher dielectric constant of Si3N4 with the same total thickness.
(a)
(b)
To exclude the electrical stress response from the bias irradiation test, the bias-induced degradation was separately measured at biases and times compared to those used during irradiation. The results show that the electrical stress has trivial influence (<5%) on compared with the TID bias irradiation effects.
Figure 3(a) shows of different gate dielectrics at different gate biases during irradiation including , , and . It can be observed that, for single gate dielectric SiO2 with different oxidation conditions, shifts all negatively, and the SiO2 layer fabricated at lower temperature presents a smaller shift at all gate biases during irradiation. It can also be observed that the threshold voltage shifts the most at irradiation bias of for single SiO2 gate dielectric. It can be explained that, at , the irradiation created holes are freely dangling around in SiO2, which are more easily trapped in the SiO2, forming positive trapped charges, leading to negative shift. For irradiation bias of , there are similar chances that irradiation created holes can be trapped in the SiO2, while, simultaneously, irradiation created electrons are swept to the SiO2/semiconductor interface, forming more interface defects than in the case of irradiation bias of , which can be confirmed by calculating, respectively, the and values by subthreshold midgap technique (SMGT) [12, 13], as is shown in Figure 3(b).
(a)
(b)
In an ideal device, the drain current and gate voltage are related by in subthreshold regime. When plotted as versus , the straight - characteristic can be extrapolated to a calculated midgap current. Comparing the preirradiation and postirradiation characteristics, the midgap voltage shift, , as well as the change in subthreshold swing (inverse slope), , can be determined. The value of is equivalent to and is proportional to . The subthreshold charge separation technique has proven to be the easiest to perform and is the most widely used. The value of is obtained from assuming the following relation: where
The difference between the pre- and postirradiation subthreshold swings, , is calculated by the following relations:where stands for the interface trap induced capacitance, is the Boltzmann constant, is the temperature, and the Fermi potential can be calculated as follows:
Figure 3(b) shows and calculated by SMGT method using (1) to (4) of both single gate dielectric SiO2 and double gate dielectric Si3N4/SiO2 at different gate bias including , , and . It can be observed that, for single SiO2 dielectric, are similar in both and , while is larger in than in , resulting in a compensation of effects.
The shifts negatively at all bias irradiation cases for single SiO2 gate dielectric layer; for double gate dielectric Si3N4/SiO2, however, shifts negatively in , and shifts positively in and barely shifts in . By calculating and , respectively, it can be observed that, at , more holes are swept towards/to the Si3N4 layer, where they can be more easily trapped compared to SiO2 [5]. For , irradiation created electrons are trapped in Si3N4, forming negative trapped charges, leading to positive shift.
Under bias irradiation, electron/hole pairs are being generated in a MOSFET. At , electrons/holes get more chances to recombine at first, forming less trapped holes and interface defects. At or , less electrons/holes recombine at higher electric field, leading to more trapped holes and interface defects, as illustrated in Figure 4.
(a)
(b)
(a)
(b)
Figures 4(a) and 4(b) show the calculated and values of both single gate dielectric SiO2 and double gate dielectric Si3N4/SiO2 at different gate bias including , , and . It can be observed that, at , single gate dielectric SiO2 and double gate dielectric Si3N4/SiO2 show similar value of , indicating similar SiO2/semiconductor interface, which is logical due to the same oxidation condition. With increasing absolute gate bias , more interface defects are created for both dielectrics.
For single gate dielectric SiO2, the oxide trapped charges increase with the absolute electric field , with the least oxide trapped charges at due to recombination of more holes/electrons at the beginning. For double gate dielectric Si3N4/SiO2, there are more net oxide trapped charges at than at , which can be explained as follows.
Under positive-bias irradiation, the charges in the SiO2 are mostly due to holes trapping at the oxide/silicon interface. In contrast to this, the negative charges due to the electrons from the oxide layer and the positive charges due to the holes from the nitride compete to determine both the magnitude and the sign of the charges in the Si3N4, as illustrated in Figure 5(a). The electrons generated in the oxide layer are swept to the nitride layer easily because no electron barrier exists at the Si3N4/SiO2 interface. The total number of holes generated in the oxide and escaping initial recombination is assumed to be approximately proportional to the oxide thickness, which is consistent with what is observed in Figure 4(a) with more in single SiO2 layer than in double Si3N4/SiO2 layer at .
For negative bias irradiation, Si3N4/SiO2 shows negative shift, larger in magnitude than that for positive-bias irradiation. This occurs because the nitride/oxide interface has more trapped holes than trapped electrons due to the holes moving from the SiO2 without hole barrier at the interface, as illustrated in Figure 5(b). Also, some of the holes generated in the oxide are trapped in the oxide. Due to the net trapping of holes in both the oxide and nitride, there is addition of charges for the negative bias case [10–13].
4. Conclusions
The gate dielectric effects and gate bias dependence of TID effects on Si VDMOS have been evaluated. Single gate dielectric SiO2 presents negative shift at either positive or negative gate bias, which improves with lower oxidation temperature. Double gate dielectric Si3N4/SiO2 shows negative shift at negative gate bias due to net holes trapping in Si3N4/SiO2 and positive shift at positive gate bias due to net electron trapping.
These results provide insight into the mechanisms and magnitude of the TID responses of Si VDMOS with SiO2 and Si3N4/SiO2 gate insulators, and Si3N4/SiO2 is proved to be more TID tolerant.
Conflicts of Interest
The authors declare that there are no conflicts of interest regarding the publication of this paper.
Authors’ Contributions
Author Min Zhou has been added as coauthor and corresponding author with all authors’ agreement. Dr. Min Zhou helps with the paper revision including paper writing and deep analysis about the microstructure of the defects responsible for trapping.
Acknowledgments
The research is supported by the National Natural Science Foundation of China (Grant 61604128), the Scientific Research Fund of Zhejiang Provincial Education Department (Grant Y201533913), and the Fundamental Research Funds for the Central Universities (Grant 2016QNA4025).