Abstract
Thorough investigations of the low-frequency noise (LFN) in a fully depleted silicon-on-insulator technology node have been accomplished, pointing out on the contribution of the buried oxide (BOX) and the Si-BOX interface to the total drain current noise level. A new analytical multilayer gate stack flat-band voltage fluctuation-based model has been established, and 2D numerical simulations have been carried out to identify the main noise sources and related parameters on which the LFN depends. The increase of the noise at strong inversion could be explained by the access resistance contribution to the 1/f noise. Therefore, considering uncorrelated noise sources in the channel and in the source/drain regions, the total low-frequency noise can simply be obtained by adding to the channel noise the contribution of the excess noise originating from the access region (Δr). Moreover, only two fit parameters are used in this work: the trap volumetric density in the BOX, and the 1/f access noise level originating from the access series resistance, which is assumed to be the same for the front and the back interfaces.
1. Introduction
Fully Depleted (FD) Silicon-On-insulator (SOI) is considered as one of the candidates for the future sub 14 nm CMOS generations. The use of ultrathin body and thin buried oxide (UTBB) enables to enhance the technology scalability, providing a very good control of the short-channel effect (SCE), as well as back-to-front gate coupling effects useful for threshold voltage Vth control with efficient body bias effect [1, 2].
The study of low-frequency noise (LF) in the UTBB FDSOI is of great interest because it is a key issue for the technology evaluation for identifying the traps possibly introduced during the device processing. Moreover, it is not only limiting the analog circuit operation, but it should also jeopardize the digital circuit functioning for aggressively scaled devices.
The analysis of LF noise in FD-SOI devices is a more complicated task compared to their bulk ancestors. In SOI instead of one interface, as in bulk devices, there are two interfaces, the so-called front and back ones, that can influence the noise behaviour due to the strong electrostatic coupling between them.
It is now well accepted that the LF 1/f noise in FDSOI and multigate devices mostly stems from the fluctuations of the inversion charge nearby the two interfaces [3–11]. For UTBB devices, the gate oxide thickness reaches dimensions as small as nanometers, leading to larger surface roughness scattering playing an important role on carrier mobility and drain current fluctuations [12].
Many studies in the past have already emphasized that the LFN should be affected by the coupling effect between the back and the front interfaces [3–11], but none of them has shown precisely by means of 2D numerically simulation the contribution of each interface on the measured total drain current noise, depending on the biasing conditions and various effective gate lengths.
In this work, our aim is first to present a rigorous investigation of the impact of back/front interface coupling effect on the low-frequency noise in UTBB FDSOI structures. For that purpose, we extend the existing carrier number fluctuations with correlated mobility fluctuations (CNF + CMF) model [11], by considering a multilayer front gate stack with existing traps in both high-k (HK) layer and an interfacial layer (IL), which are uniformly distributed in the energy gap and space.
This new model, although simple, is applied successfully to strongly coupled FDSOI devices, including correlated mobility fluctuations for the channel noise and the access noise originating from the Source and Drain regions (CNF + CMF+Δr), thus significantly going beyond previous works [3–11].
2. Experimental Details
The MOS devices used in this study are n-channel FDSOI fabricated by ST Microelectronics (France) with interfacial layer/high-k (IL-HK) and metal gate which were made on (100) SOI wafers with 25 nm BOX. The silicon film thickness under the gate is 7 nm. The IL-HK gate oxide stack has a capacitance equivalent thickness (CET) of about 1.6 nm [13]. The gate mask width is 1 μm, and mask gate length is varying from 30 nm to 1 μm. A typical cross section of the FDSOI structure is shown in Figure 1 [13].
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Static I–V measurements were carried out as a function of drain and gate voltages using an HP 4156b semiconductor parameter analyzer. The FDSOI parameters have been extracted in linear regime (Vd = 20 mV) using the McLarty technique [14], especially designed for extracting the MOSFET parameters with strong mobility degradation quadratic factor θ2. In addition, the C-V measurements were taken out from HP 4294A impedance-meter with a 40 mV small signal at 1 MHz, which allows extraction of the gate length reduction ΔL = 15 nm for such devices [15].
The LF noise measurements were carried out at room temperature using a programmable Pin-Probe Noise Measuring System (3PNMS) with Elite 300 probe station. The noise measurement bandwidth is from 1 Hz to 10 kHz. Note that the noise data below 10 Hz are not meaningful due to AC filtering in the noise measuring system.
3. Static Characterization of FDSOI Devices
With the front gate conduction mode, in linear region, the drain current for front gate (noted as 1), operated from weak to strong inversion, is given bywhere W and L are the effective channel width and length, respectively, Qi1 is the inversion charge density, μeff1 is the effective mobility, and Vd is the drain voltage.
In order to consider either surface roughness effects which increase rapidly with vertical field, phonon scattering effects, and series resistance effects, the effective mobility μeff1 can be expressed as [12]where μ0 is the low field mobility, θ1 and θ2 are the mobility degradation parameters, and Vth1 is the threshold voltage. Table 1 illustrates static parameters for 0 V back gate, extracted for various mask gate lengths LM and gate mask width WM of 1 μm. It is worth noting that the mobility degradation parameter θ1 is affected by series resistance and is given by the following relation [16]: = θ1+Gm·RSD, where Gm = Coxµ0W/L. Therefore, the plot of as a function of Gm give a straight line, from which the slope provides parasitic resistance RSD and y-axis intercept factor θ1. Note that, looking at Table 1, the negative value of θ1 is representative of an increasing mobility at small gate voltage drive due to significant Coulomb scattering contribution [12]. Moreover, θ2 varies only on a very small range between 0.521 and 0.667, leading to a quasiconstant surface roughness effects for the transistors various gate lengths (Lm (nm) = 30, 35, 40, 120, 300, 1000), and a fixed gate width (Wm = 1 μm).
4. Low-Frequency Noise in FDSOI Devices at Ohmic Operation
4.1. Semianalytical (CNF + CMF+Δr) 1/f Noise Model
By using the flat-band voltage fluctuations theory [17], δVfb1,2 = −δQox1,2/Cox1,2 due to the oxide and/or interface charge fluctuations δQox1,2 as well as to the effective mobility fluctuations δµeff1,2, and also taking into account the access series resistance fluctuations, one gets for the drain current variations δId for each interface [8, 10, 12]:
The effective mobility μeff1,2 is given by [10]where α1,2 is the Coulomb scattering parameter. Knowing that the transconductance definition is = = −δId/δVfb1,2, equations (7a)–(8) yield
After accounting for the noise in the access resistance as in [18], the normalized spectral density of drain current can then be expressed as [8, 10]where SRsd1,2 is the power spectral density (PSD) of source-drain series resistance for front and the back gate interfaces. Since the access resistance RSD is the same for interface 1 and 2, then SRsd1 = SRsd2 = SRsd.
As the multilayer front gate stack contains a high-k layer (HK), and an oxide interfacial layer (IL), traps are in both layers, so the tunnelling distance and trap volumetric density should be considered accordingly. Hence, the flat-band spectral density is split into two terms, each referring to a given layer. Thereby, our new model is modified in order to include the effect of both gate stack layers having different charge centroid such aswhere C1,hk refers to the capacitance of the HK layer, Nt1,ox is the volumetric oxide trap densities in the oxide interfacial layer, Nt1,hk the volumetric oxide trap densities in the high k dielectric layer, Nt2 is the volumetric oxide trap density in the BOX, λil and λhk are the tunnelling distances in the oxide IL and KH layer, respectively, q is the electron charge, kT is the thermal energy and f is the measuring frequency. In our 2D simulations analysis, we have assumed that Nt2 is equal to Nt1il, because the BOX is a pure silicon oxide as the IL. Furthermore, the traps are considered uniformly distributed in energy. The front gate stack consists of TiN/Hf-based oxide dielectric with equivalent oxide thickness tox = 1.6 nm, while the silicon film thickness tSi is 7 nm, and the BOX thickness is 25 nm [13].
5. 2D Numerical Simulation
5.1. FDSOI Devices under Study
To verify the accuracy of the proposed semianalytical (CNF + CMF+Δr) 1/f noise model, the electric potential V, and the quasi-Fermi level Uc distribution, within the silicon film (Si), both along the channel (x-direction), and along the depth of the Si film (y-direction), are simulated using FlexPDE software, which solves partial differential equations based on finite elements method [19]. The program solves numerically the 2D Poisson equation coupled to drift-diffusion current continuity equations, within a specific mesh, and corresponding boundaries conditions of the structure described in Figure 1(b). Quantum confinement effects for the carriers within the two interfaces are taken into account thanks to the Hänsch model adapted to the FDSOI structure [20].
For an appropriate comparative study, three devices with a gate width equal to 1 μm and different effective channel lengths (L = 985, 105, and 15 nm). Based on the extracted parameters of Table 1, the 2D simulation results of Ids-Vgs characteristics is shown in Figure 2 and exhibit very good agreement with experimental data.
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Note from Figure 2(b) that the 2D potential distribution of the shortest transistor induces unwanted short-channel effect such as degradation of Ids-Vgs transfer characteristics below threshold voltage. In addition, the rising contribution of series resistance causes a drastic decrease in mobility, by impacting the intrinsic factor θ1. Therefore, reducing the series resistance of the source-drain junction is a major concern for improving the performance of the advanced FDSOI MOSFET.
5.2. 2D Numerical Modelling of Remote Coulomb Scattering
In order to account for CMF in (4), it is suitable to consider the remote Coulomb scattering (RCS) parameter, across the silicon film, proper for each interface. Thus, we consider the RCS coefficient α1,2 for both interfaces given by [21]where a0 is approximately 105 Vs/C for this UTBB SOI technology [21], and λc = 1.2 nm, y is the average distance between the inversion charge distribution centroid and the front interface, whereas tSI-y is the distance of the inversion charge distribution centroid from the back interface.
A clear overview of the RCS factors variations as a function of VFG are shown in Figure 3. Since the front gate conduction mode is considered, the charge is mostly concentrated near the front interface, giving rise to an increase of α1, as much as the transistor is shorter (Figure 3(a)). Regarding α2 (Figure 3(b)), on the contrary, it decreases as much as the size of the transistor is smaller, when VFG goes from weak to strong inversion. Thus, antagonistic roles are played by α1 and α2 in this front gate mode of operation, giving rise to α1 values, which are, at least, an order of magnitude greater than those of α2.
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Therefore, Figure 4 shows α1,2 RCS parameters from which a strong coupling effect between the two interfaces is evidenced, even when the back gate is grounded (VBG = 0 V).
5.3. 2D LF Noise Numerical Results and Discussion
The noise measurements was carried out for various devices from 1 Hz to 10 KHz, with drain voltage Vd = 20 mV and gate voltage varied from weak to strong inversion. Figure 4 illustrates typical 1/f normalized drain current PSD for NMOS FDSOI with effective gate length L = 105 nm, and for different VGF, and VGB = 0 V. The general LFN behaviour exhibits 1/fγ behaviour, with γ exponent ≈0.9–1.1, for all the range of VGF going from 0.15 V to 0.65 V, for frequency lower than 100 Hz, and for not very short-channel devices.
At first sight, the normalized drain current noise versus drain current characteristics (Figure 5(a)) measured in front gate mode follows the overall evolution of the squared transistor gain (/Id1,2)2 [17, 18], indicating that the LF noise can mostly be interpreted by CNF noise model.
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Figure 5(b) illustrates the corresponding front input-referred voltage noise and following the general SId/ tendency. Previous works have shown that the LF noise in FDSOI devices should be influenced by coupling effect between back and front interfaces [3–11]. Due to this coupling, it is difficult to predict precisely the contribution of each interface on the measured overall noise level, or contribution of back interface with respect to that of front interface. Therefore, analytical study of the noise sources and their dependence on the bias conditions is critical for the UTBB FDSOI MOSFETS.
In order to show and discuss the 2D numerical simulation results of LF noise, it is suitable to input from Table 2 the main parameters which are required by the TCAD tool. In fact, only two fitting parameters are used in this study in order to fit the experimental data. The parameters Nt1 for each transistor are taken from [10, 13], while the corresponding Nt2 are used as fitting parameters. The second fitting parameter is the access resistance noise level Kr.
We can notice that the volumetric trap density associated to IL/HK layer is approximately two orders of magnitude higher than the ones associated to the BOX layer, which is widely reported in many papers [3–10, 22, 23], in state-of-the art devices.
Our aim is to compare the two 2D numerical LF noise models (CNF + Δr) and (CNF + CMF + Δr), on one hand, and, on the other hand, the semianalytical model, which is based on equations (1)–(7b) of Section 4, with experimental data. Note that the two models include the LF noise originated from the access series resistance RSD, whose impact should become increasingly important for next generations, sub 10 nm FDSOI devices.
Figure 6 represents the normalized current noise spectral density (SId/) for the front channel, where (a) 2D numerical models (CNF+Δr), and (b) (CNF + CMF + Δr) are both compared to data, whereas in (c), the semianalytical model is also compared to data.
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As indicated in equation (6), a very important parameter for flicker noise analysis in MOSFETs is the squared transistor gain (/Id)2, computed here in 2D simulation for front gate operation, with VBG = 0 V, as a function of drain current. As it is usual, it exhibits (Figure 6) a plateau in weak inversion, before dropping above threshold in strong inversion, indicating that the LF noise is due fundamentally to carrier number fluctuations [17, 18].
Furthermore, a very useful parameter in FDSOI devices is the coupling factor c2 which expresses the relative impact of each interface on LF noise level. It is given by [3, 4, 8–10]
As it can be seen from Figure 7, the coupling factor c2 is about 1.24 and 1.15 at drain current Id1 = 5 μA, for devices with gate length L = 105 nm, and 985 nm, respectively, with the back interface biased in depletion mode, whereas the front interface goes from weak to strong inversion. This feature points out the great importance of the back interface LF noise contribution. Moreover, we can notice that c2 decreases very quickly for the shortest device passing from about 0.49 at Id1 = 5 μA, to 0.03 at 80 μA, indicating that the short-channel effects may affect the back LF noise contribution, making it less predominant at strong inversion. However, for a better understanding, the latter observation needs to be validated by other experiments and simulations on different advanced FDSOI devices.
Thus, although the coupling factor c2, at Id1 = 5 μA, appears to be lying between 1.24 and 1.12 for the effective gate lengths L = 105 nm and L = 985 nm, respectively, it becomes more important when multiplied by the SVfb2/SVfb1 ratio, showing the importance of the coupling effect in these devices, when the front interface is stepping from weak to strong inversion, and the back interface is biased at zero volt.
Looking at Figure 7, it will be noted that, in general, the coupling factor c2 tends to decrease as a function of the Id1 current, showing that, in strong inversion, the decoupling of the back interface becomes more and more important. This effect is even more pronounced for the shorter transistor. However, when operating in back gate mode, this situation is reversed completely, and the back gate contribution becomes more significant at strong inversion.
Regarding Figure 6, the two 2D numerical simulations results from CNF + CMF + Δr, and CNF + Δr models, and the semianalytical model based on the CNF + CMF + Δr model are presented. Thus, using RCS formulation of equation (8) in the CNF LF noise model of equation (6) leading to CNF + CMF noise model, on one hand, and including also LF noise originated from the access series resistance RSD, on the other hand (CNF + CMF + Δr), the variations of SId/Id2 with drain current are well described, and agree perfectly well with the experimental data.
Recalling that only two physical entities are used as fitting parameters, the other parameters are either taken from Tables 1–3 or extracted from experimental data. Using these parameters also enables to describe well the dependence of the normalized drain current noise SId/Id2 as a function of drain current Id for varying from weak to strong inversion regions as shown in Figure 6. Note that the buried oxide traps which are lying in the range of 1–3 × 1015/eV/cm3 are extremely low, confirming the very good quality of a pure thermal oxide, and the front interface traps density are almost two decades higher due to the IL/high-k/metal gate stack [3–10, 22, 23].
For the sake of the modelling precision, Figure 8 shows the comparison between experimental plots of SVg versus (-Vth)/[1-θ2∙(-Vth)2] with (a) CNF + CMF + Δr, 2D numerical simulation results, with RCS parameters, and (b) with the corresponding semianalytical model, just as in Figure 7.
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We can notice that the 2D simulation corresponding to Figure 8(a) is very similar to the model corresponding to Figure 8(b) and presents the best results for the overall tested devices.
At the lowest applied front gate voltage ( < Vth), the total input-referred noise SVg for L = 105 nm and L = 985 nm is quasiconstant, clearly indicating that the carrier number fluctuations due to carrier trapping in the oxide layer dominate the 1/f noise [17, 18]. The increase of the noise in strong inversion could be explained by the correlated mobility fluctuations (CNF + CMF). The huge rise in noise level can be attributed to the influence of the access series resistance RSD [18]. For the shortest device, one can notice a decrease in the noise level in weak inversion, and this feature is probably due to the importance of coupling factor c2 weighted by SVfb2/SVfb1 as shown in Table 3.
5.4. Front Interface Noise Level to the Total Noise Level Ratio R1
Figure 9 illustrates the R1 factor defined as the ratio of contribution of the front interface noise level to the total noise level ones: (SId/Id2)1/(SId/Id2)tot, according to the (CNF + Δr) model (Figure 9(a)), and then according to (CNF + CMF + Δr) model (Figure 9(b)).
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In Figure 9(a), for the CNF + Δr model, it can be seen that for all channel geometries, the ratio R1 varies between 0.1% in weak inversion, up to about 50% in strong inversion, showing a more significant contribution of the front interface, at high gate voltage, but without exceeding the noise level related to the back interface.
For the CNF + CMF + Δr model, illustrated in Figure 9(b), the situation is quite similar to that of the previous case, except that the noise contribution percentage has somewhat changed. Now it passes from 0.2% to 75%, showing that an additional 25% arises here, compared to the previous case, in strong inversion, from the correlated mobility fluctuations phenomena. These results therefore confirms the general feature of the normalized PSD at 10 Hz of the drain current fluctuations induced by each interface oxide traps density and the total normalized drain current fluctuations as is illustrated for one gate length in Figure 10, by plotting SId/Id2 versus drain current, in the front gate operating mode [8–10].
Figure 10 shows the normalized drain current fluctuations extracted at 10 Hz, induced by each oxide traps related to both interfaces 1 and 2, and the total normalized drain current fluctuations. These simulations were performed with volumetric trap densities and gate lengths geometries which are mentioned in Table 2. The front gate operating mode is considered.
As a result, though the front interface trap density are almost two decades higher to those of the back interface, the total noise level is completely dominated by the back interface noise contribution in the weak and intermediate inversion operation, whereas the situation tends to reverse or at least to balance in strong inversion operation as shown in Figure 10.
Note again that the plateau observed in weak inversion, for all the studied devices, indicates that the CNF model due to carrier trapping in the oxide layer dominates, whereas in the intermediate and strong inversion, the CNF + CMF model is more appropriate. From onset until the end of the strong inversion operation, the level noise increase is perfectly explained by the access resistance contribution to the 1/f noise.
6. Conclusion
A new extended 1/f noise model (CNF + CMF + Δr) related to double-layer high-k gate stacks devices has been formulated, considering the trap volumetric density in both IL and HK dielectric layers. The previous models [8–11] remain valid overall, but only if the IL thickness is large compared to that of the HK one, which is not the case for our studied devices.
Moreover, a detailed analysis both in semianalytical modelling and 2D numerical simulations has been carried out to identify the main noise sources and related parameters in advanced FDSOI devices. Thus, this improved semianalytical 1/f noise model called (CNF + CMF + Δr) is based on the carrier number fluctuations with correlated mobility fluctuations enhanced with LF noise originated from the access series resistance RSD. It has been successfully validated through experimental data and 2D numerical simulation results obtained on FDSOI devices. Finally, we have pointed out that the total noise is dominated by the buried oxide noise level contribution, for the whole voltage range of the front gate operation mode, as a result of the strong back-to-front coupling in such UTBB FDSOI devices.
Data Availability
The figure data used to support the findings of this study are not available.
Conflicts of Interest
The authors declare that there are no conflicts of interest regarding the publication of this paper.
Acknowledgments
This work was performed with the support of author’s employers, i.e., CNRS for G. Ghibaudo and Univ. of Oran for T. Boutchacha.