Active and Passive Electronic Components The latest articles from Hindawi © 2018 , Hindawi Limited . All rights reserved. VHDL-AMS Simulation Framework for Molecular-FET Device-to-Circuit Modeling and Design Mon, 01 Jan 2018 00:00:00 +0000 We concentrate on Molecular-FET as a device and present a new modular framework based on VHDL-AMS. We have implemented different Molecular-FET models within the framework. The framework allows comparison between the models in terms of the capability to calculate accurate - characteristics. It also provides the option to analyze the impact of Molecular-FET and its implementation in the circuit with the extension of its use in an architecture based on the crossbar configuration. This analysis evidences the effect of choices of technological parameters, the ability of models to capture the impact of physical quantities, and the importance of considering defects at circuit fabrication level. The comparison tackles the computational efforts of different models and techniques and discusses the trade-off between accuracy and performance as a function of the circuit analysis final requirements. We prove this methodology using three different models and test them on a 16-bit tree adder included in Pentium 4 that, to the best of our knowledge, is the biggest circuits based on molecular device ever designed and analyzed. Mariagrazia Graziano, Ali Zahir, Malik Ashter Mehdy, and Gianluca Piccinini Copyright © 2018 Mariagrazia Graziano et al. All rights reserved. A Self-Biased Active Voltage Doubler for Energy Harvesting Systems Sun, 03 Dec 2017 10:06:07 +0000 An active voltage doubler utilizing a single supply op-amp for energy harvesting system is presented. The proposed doubler is used for rectification process to achieve both acceptably high power conversion efficiency (PCE) and large rectified DC voltage. The incorporated op-amp is self-biased, meaning no external supply is needed but rather it uses part of the harvested energy for its biasing. The proposed active doubler achieves maximum power conversion efficiency (PCE) of 61.7% for a 200 Hz sinusoidal input of 0.8 V for a 20 K load resistor. This efficiency is 2 times more when compared with the passive voltage doubler. The rectified DC voltage is almost 2 times more than conventional passive doubler. The relation between PCE and the load resistor is also presented. The proposed active voltage doubler is designed and simulated in LF 0.15 μm CMOS process technology using Cadence virtuoso tool. Umais Tayyab and Hussain A. Alzaher Copyright © 2017 Umais Tayyab and Hussain A. Alzaher. All rights reserved. Low-Power CMOS Integrated Hall Switch Sensor Tue, 07 Nov 2017 06:31:08 +0000 This paper presents an integrated Hall switch sensor based on SMIC 0.18 µm CMOS technology. The system includes a front-end Hall element and a back-end signal processing circuit. By optimizing the structure of the Hall element and using the orthogonal coupling and spinning current technology, the offset voltage can be suppressed effectively. The simulation results showed that the Hall switch can eliminate offset voltage greater than 1 mV at 3.3 V supply voltage. Two modes of the Hall switch circuit, the awake mode and the sleep mode, were realized by using clock logic signals without compromising the performance of the Hall switch, thereby reducing power consumption. The test results showed that the operate point and the release point of the switch were within the range of 3–7 mT at 3.3 V supply voltage. Meanwhile, the current consumption is 7.89 µA. Rongshan Wei, Shizhong Guo, and Shanzhi Yang Copyright © 2017 Rongshan Wei et al. All rights reserved. A Novel Floating Memristor Emulator with Minimal Components Thu, 19 Oct 2017 00:00:00 +0000 A new floating emulator for the flux-controlled memristor is introduced in this paper. The proposed emulator circuit is very simple and consists of only two current feedback operational amplifiers (CFOAs), two analog multipliers, three resistors, and two capacitors. The emulator can be configured as an incremental or decremental type memristor by using an additional switch. The mathematical model of the emulator is derived to characterize its behavior. The hysteresis behavior of the emulator is discussed in detail, showing that the pinched hysteresis loops in - plane depend not only on the amplitude-to-frequency ratio of the exciting signal but also on the time constant of the emulator circuit itself. Experimental tests are provided to validate the emulator’s workability. Zhijun Li, Yicheng Zeng, and Minglin Ma Copyright © 2017 Zhijun Li et al. All rights reserved. Total Ionizing Dose Effects of Si Vertical Diffused MOSFET with SiO2 and Si3N4/SiO2 Gate Dielectrics Sun, 15 Oct 2017 00:00:00 +0000 The total ionizing dose irradiation effects are investigated in Si vertical diffused MOSFETs (VDMOSs) with different gate dielectrics including single SiO2 layer and double Si3N4/SiO2 layer. Radiation-induced holes trapping is greater for single SiO2 layer than for double Si3N4/SiO2 layer. Dielectric oxidation temperature dependent TID effects are also studied. Holes trapping induced negative threshold voltage shift is smaller for SiO2 at lower oxidation temperature. Gate bias during irradiation leads to different shift for different gate dielectrics. Single SiO2 layer shows the worst negative at , while double Si3N4/SiO2 shows negative shift at , positive shift at , and negligible shift at . Jiongjiong Mo, Xuran Zhao, and Min Zhou Copyright © 2017 Jiongjiong Mo et al. All rights reserved. Power Device Thermal Fault Tolerant Control of High-Power Three-Level Explosion-Proof Inverter Based on Holographic Equivalent Dual-Mode Modulation Mon, 02 Oct 2017 00:00:00 +0000 It is necessary for three-level explosion-proof inverters to have high thermal stability and good output characteristics avoiding problems caused by power devices, such as IGBT, so it becomes a hot and difficult research point using only one control algorithm to guarantee both output characteristics and high thermal stability. Firstly, the simplified SVPWM (Space Vector Pulse Width Modulation) algorithm was illustrated based on the NPC (neutral-point-clamped) three-level inverter, and then the quasi-square wave control was brought in and made into a novel holographic equivalent dual-mode modulation algorithm together with the simplified SVPWM. The holographic equivalent model was established to analyze the relative advantages comparing with the two single algorithms. Finally, the dynamic output and steady power device losses were analyzed, based on which the power loss calculation and system simulation were conducted as well. The experiment proved that the high-power three-level explosion-proof inverter has good output characteristics and thermal stability. Shi-Zhou Xu, Chun-jie Wang, and Yu-feng Peng Copyright © 2017 Shi-Zhou Xu et al. All rights reserved. Investigation and Analysis of the Simultaneous Switching Noise in Power Distribution Network with Multi-Power Supplies of High Speed CMOS Circuits Thu, 28 Sep 2017 00:00:00 +0000 The paper studies a simultaneous switching noise (SSN) in a power distribution network (PDN) with dual supply voltages and two cores. This is achieved by reducing the admittance matrix of the PDN then calculating frequency domain impedance with rational function approximation using vector fitting. This paper presents a method of computing the simultaneous switching noise through a switching current, whose properties and details are described. Thus, the results are discussed and performed using MATLAB and PSpice tools. It demonstrated that the presence of many cores in the same PCB influences the SSN due to electromagnetic coupling. Khaoula Ait Belaid, Hassan Belahrach, and Hassan Ayad Copyright © 2017 Khaoula Ait Belaid et al. All rights reserved. All-Pass Filter Based Linear Voltage Controlled Quadrature Oscillator Tue, 29 Aug 2017 00:00:00 +0000 A linear voltage controlled quadrature oscillator implemented from a first-order electronically tunable all-pass filter (ETAF) is presented. The active element is commercially available current feedback amplifier (AD844) in conjunction with the relatively new Multiplication Mode Current Conveyor (MMCC) device. Electronic tunability is obtained by the control node voltage () of the MMCC. Effects of the device nonidealities, namely, the parasitic capacitors and the roll-off poles of the port-transfer ratios of the device, are shown to be negligible, even though the usable high-frequency ranges are constrained by these imperfections. Subsequently the filter is looped with an electronically tunable integrator (ETI) to implement the quadrature oscillator (QO). Experimental responses on the voltage tunable phase of the filter and the linear-tuning law of the quadrature oscillator up to 9.9 MHz at low THD are verified by simulation and hardware tests. Koushick Mathur, Palaniandavar Venkateswaran, and Rabindranath Nandi Copyright © 2017 Koushick Mathur et al. All rights reserved. Design of 0.8–2.7 GHz High Power Class-F Harmonic-Tuned Power Amplifier with Parasitic Compensation Circuit Wed, 14 Jun 2017 06:50:47 +0000 The design, implementation, and measurements of a high efficiency and high power wideband GaN HEMT power amplifier are presented. Package parasitic effect is reduced significantly by a novel compensation circuit design to improve the accuracy of impedance matching. An improved structure is proposed based on the traditional Class-F structure with all even harmonics and the third harmonic effectively controlled, respectively. Also the stepped-impedance matching method is applied to the third harmonic control network, which has a positive effect on the expansion bandwidth. CGH40025F power transistor is utilized to build the power amplifier working at 0.8 to 2.7 GHz, with the measured saturated output power 20–50 W, drain efficiency 52%–76%, and gain level above 10 dB. The second and the third harmonic suppression levels are maintained at −16 to −36 dBc and −16 to −33 dBc, respectively. The simulation and the measurement results of the proposed power amplifier show good consistency. Zhiqun Cheng, Xuefei Xuan, Huajie Ke, Guohua Liu, Zhihua Dong, and Steven Gao Copyright © 2017 Zhiqun Cheng et al. All rights reserved. Less-Conventional Low-Consumption Galvanic Separated MOSFET-IGBT Gate Drive Supply Wed, 24 May 2017 00:00:00 +0000 A simple half-bridge, galvanic separated power supply which can be short circuit proof is proposed for gate driver local supplies. The supply is made while hacking a common mode type filter as a transformer, as the transformer shows a good insulation, it has a very low parasitic capacitance between primary and secondary coils, and it is cost-effective. Very low standby losses were observed during lab experiments. This makes it compatible with energy efficient drives and solar inverters. Jean Marie Vianney Bikorimana and Alex Van den Bossche Copyright © 2017 Jean Marie Vianney Bikorimana and Alex Van den Bossche. All rights reserved. Three-Input Single-Output Voltage-Mode Multifunction Filter with Electronic Controllability Based on Single Commercially Available IC Mon, 03 Apr 2017 00:00:00 +0000 This paper presents a second-order voltage-mode filter with three inputs and single-output voltage using single commercially available IC, one resistor, and two capacitors. The used commercially available IC, called LT1228, is manufactured by Linear Technology Corporation. The proposed filter is based on parallel RLC circuit. The filter provides five output filter responses, namely, band-pass (BP), band-reject (BR), low-pass (LP), high-pass (HP), and all-pass (AP) functions. The selection of each filter response can be done without the requirement of active and passive component matching condition. Furthermore, the natural frequency and quality factor are electronically controlled. Besides, the nonideal case is also investigated. The output voltage node exhibits low impedance. The experimental results can validate the theoretical analyses. Supachai Klungtong, Dusit Thanapatay, and Winai Jaikla Copyright © 2017 Supachai Klungtong et al. All rights reserved. Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET Tue, 21 Mar 2017 00:00:00 +0000 Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio (), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET. Satyam Shukla, Sandeep Singh Gill, Navneet Kaur, H. S. Jatana, and Varun Nehru Copyright © 2017 Satyam Shukla et al. All rights reserved. A New CMOS Controllable Impedance Multiplier with Large Multiplication Factor Tue, 07 Mar 2017 00:00:00 +0000 This paper presents a new compact controllable impedance multiplier using CMOS technology. The design is based on the use of the translinear principle using MOSFETs in subthreshold region. The value of the impedance will be controlled using the bias currents only. The impedance can be scaled up and down as required. The functionality of the proposed design was confirmed by simulation using BSIM3V3 MOS model in Tanner Tspice 0.18 μm TSMC CMOS process technology. Simulation results indicate that the proposed design is functioning properly with a tunable multiplication factor from 0.1- to 100-fold. Applications of the proposed multiplier in the design of low pass and high pass filters are also included. Munir A. Al-Absi Copyright © 2017 Munir A. Al-Absi. All rights reserved. Microwave Impedance Spectroscopy and Temperature Effects on the Electrical Properties of Au/BN/C Interfaces Sun, 26 Feb 2017 08:55:36 +0000 In the current study, an Au/BN/C microwave back-to-back Schottky device is designed and characterized. The device morphology and roughness were evaluated by means of scanning electron and atomic force microscopy. As verified by the Richardson–Schottky current conduction transport mechanism which is well fitted to the experimental data, the temperature dependence of the current-voltage characteristics of the devices is dominated by the electric field assisted thermionic emission of charge carriers over a barrier height of ~0.87 eV and depletion region width of ~1.1 μm. Both the depletion width and barrier height followed an increasing trend with increasing temperature. On the other hand, the alternating current conductivity analysis which was carried out in the frequency range of 100–1400 MHz revealed the domination of the phonon assisted quantum mechanical tunneling (hopping) of charge carriers through correlated barriers (CBH). In addition, the impedance and power spectral studies carried out in the gigahertz-frequency domain revealed a resonance-antiresonance feature at frequency of  ~1.6 GHz. The microwave power spectra of this device revealed an ideal band stop filter of notch frequency of  ~1.6 GHz. The ac signal analysis of this device displays promising characteristics for using this device as wave traps. Hazem K. Khanfar, A. F. Qasrawi, and Yasmeen Kh. Ghannam Copyright © 2017 Hazem K. Khanfar et al. All rights reserved. Design of a SIW Bandpass Filter Using Defected Ground Structure with CSRRs Sun, 29 Jan 2017 00:00:00 +0000 In this paper, a substrate integrated waveguide (SIW) bandpass filter using defected ground structure (DGS) with complementary split ring resonators (CSRRs) is proposed. By using the unique resonant properties of CSRRs and DGSs, two passbands with a transmission zero in the middle have been achieved. The resonant modes of the two passbands are different and the bandwidth of the second passband is much wider than that of the first one. In order to increase out-of-band rejection, a pair of dumbbell DGSs has been added on each side of the CSRRs. The structure is analyzed using equivalent circuit models and simulated based on EM simulation software. For validation, the proposed filter is fabricated and measured. The measurement results are in good agreement with the simulated ones. Weiping Li, Zongxi Tang, and Xin Cao Copyright © 2017 Weiping Li et al. All rights reserved. Design Impedance Mismatch Physical Unclonable Functions for IoT Security Tue, 24 Jan 2017 00:00:00 +0000 We propose a new design, Physical Unclonable Function (PUF) scheme, for the Internet of Things (IoT), which has been suffering from multiple-level security threats. As more and more objects interconnect on IoT networks, the identity of each thing is very important. To authenticate each object, we design an impedance mismatch PUF, which exploits random physical factors of the transmission line to generate a security unique private key. The characteristic impedance of the transmission line and signal transmission theory of the printed circuit board (PCB) are also analyzed in detail. To improve the reliability, current feedback amplifier (CFA) method is applied on the PUF. Finally, the proposed scheme is implemented and tested. The measure results show that impedance mismatch PUF provides better unpredictability and randomness. Xiaomin Zheng, Yuejun Zhang, Jiaweng Zhang, and Wenqi Hu Copyright © 2017 Xiaomin Zheng et al. All rights reserved. Operational Simulation of LC Ladder Filter Using VDTA Mon, 23 Jan 2017 00:00:00 +0000 In this paper, a systematic approach for implementing operational simulation of LC ladder filter using voltage differencing transconductance amplifier is presented. The proposed filter structure uses only grounded capacitor and possesses electronic tunability. PSPICE simulation using 180 nm CMOS technology parameter is carried out to verify the functionality of the presented approach. Experimental verification is also performed through commercially available IC LM13700/NS. Simulations and experimental results are found to be in close agreement with theoretical predictions. Praveen Kumar, Neeta Pandey, and Sajal Kumar Paul Copyright © 2017 Praveen Kumar et al. All rights reserved. A New Capacitor-Less Buck DC-DC Converter for LED Applications Tue, 17 Jan 2017 06:00:28 +0000 In this paper, a new capacitor-less DC-DC converter is proposed to be used as a light emitting diode (LED) driver. The design is based on the utilization of the internal capacitance of the LED to replace the smoothing capacitor. LED lighting systems usually have many LEDs for better illumination that can reach multiple tens of LEDs. Such configuration can be utilized to enlarge the total internal capacitance and hence minimize the output ripple. Also, the switching frequency is selected such that a minimum ripple appears at the output. The functionality of the proposed design is confirmed experimentally and the efficiency of the driver is 85% at full load. Munir Al-Absi, Zainulabideen Khalifa, and Alaa Hussein Copyright © 2017 Munir Al-Absi et al. All rights reserved. Simultaneous Suppression of IMD3 and IMD5 in Space TWT by IMD3 and 2HD Signal Injection Tue, 10 Jan 2017 00:00:00 +0000 This paper presents a signal injection technology showing significant reductions in both 3rd-order and 5th-order intermodulation distortions (IMD3 and IMD5) in space traveling wave tube (STWT). By applying the IMD3 to the IMD5 ratio (TFR) as measures of location, the simultaneous suppressions of IMD3 and IMD5 in TWT are achieved by second harmonic distortion (2HD) and IMD3 injection. According to the research on theoretical analysis and computer simulation, the optimum amplitude and phase parameters of the injected signal for maximum simultaneous suppressions are obtained. Then an experiment system is established based on vector network analyzer, optimum TFR are 2.1 dB and 12.5 dB, respectively, by second harmonic and IM3 injection, and the output powers of IMD3 and IMD5 were decreased. TFR with IMD3 injection is smaller than that with second harmonic injection in STWT, and the experiment system is more straightforward and easy to operate. Thus, the IMD3 injection performs better than that of second harmonic injection to suppress IMD5s for the narrow-band STWT. Dongming Zhao, Huijuan Liu, Kewen Xia, Shi Li, and Xiaoxu Shi Copyright © 2017 Dongming Zhao et al. All rights reserved. Design of a Narrow Bandwidth Bandpass Filter Using Compact Spiral Resonator with Chirality Mon, 26 Dec 2016 06:28:40 +0000 In this article, a compact narrow-bandpass filter with high selectivity and improved rejection level is presented. For miniaturization, a pair of double negative (DNG) cells consisting of quasi-planar chiral resonators are cascaded and electrically loaded to a microstrip transmission line; short ended stubs are introduced to expand upper rejection band. The structure is analyzed using equivalent circuit models and simulated based on EM simulation software. For validation, the proposed filter is fabricated and measured. The measured results are in good agreement with the simulated ones. By comparing to other filters in the references, it is shown that the proposed filter has the advantage of skirt selectivity and compact size, so it can be integrated more conveniently in modern wireless communication systems and microwave planar circuits. Weiping Li, Zongxi Tang, and Xin Cao Copyright © 2016 Weiping Li et al. All rights reserved. Impact of Band Nonparabolicity on Threshold Voltage of Nanoscale SOI MOSFET Sun, 25 Dec 2016 09:42:11 +0000 This paper reconsiders the mathematical formulation of the conventional nonparabolic band model and proposes a model of the effective mass of conduction band electrons including the nonparabolicity of the conduction band. It is demonstrated that this model produces realistic results for a sub-10-nm-thick Si layer surrounded by an SiO2 layer. The major part of the discussion is focused on the low-dimensional electron system confined with insulator barriers. To examine the feasibility of our consideration, the model is applied to the threshold voltage of nanoscale SOI FinFETs and compared to prior experimental results. This paper also addresses a model of the effective mass of valence band holes assuming the nonparabolic condition. Yasuhisa Omura Copyright © 2016 Yasuhisa Omura. All rights reserved. Computer and Hardware Modeling of Periodically Forced -Van der Pol Oscillator Thu, 15 Dec 2016 14:09:49 +0000 Numerical simulation results for the dynamics of -systems abound in the literature but their experimental results are yet to be known. This paper presents the chaotic dynamics of -Van der Pol oscillator via electronic design, simulation, and hardware implementation. The results obtained are found to be in good agreement with numerical simulation results. The condition for stability of the fixed points is also computed and the method of multiple time scale is used to investigate the dynamical behaviour of the system. Therefore, the -circuits which have rich dynamics and may have important applications in secure communications, random number generations, cryptography, and so forth have been practically implemented. A. O. Adelakun, A. N. Njah, O. I. Olusola, and S. T. Wara Copyright © 2016 A. O. Adelakun et al. All rights reserved. Semiconductors: Materials, Physics, and Devices Thu, 15 Dec 2016 10:31:07 +0000 Jiangwei Liu, Hongyang Zhao, Jinlong Liu, Aurélien Maréchal, and Wei Wang Copyright © 2016 Jiangwei Liu et al. All rights reserved. Apodization Optimization of FBG Strain Sensor for Quasi-Distributed Sensing Measurement Applications Sun, 04 Dec 2016 11:15:16 +0000 A novel optimized apodization of Fiber Bragg Grating Sensor (FBGS) for quasi-distributed strain sensing applications is developed and introduced in this paper. The main objective of the proposed optimization is to obtain a reflectivity level higher than 90% and a side lobe level around −40 dB, which is suitable for use in quasi-distributed strain sensing application. For this purpose, different design parameters as apodization profile, grating length, and refractive index have been investigated to enhance and optimize the FBGS design. The performance of the proposed apodization has then been compared in terms of reflectivity, side lobe level (SLL), and full width at half maximum (FWHM) with apodization profiles proposed by other authors. The optimized sensor is integrated on quasi-distributed sensing system of 8 sensors demonstrating high reliability. Wide strain sensitivity range for each channel has also been achieved in the quasi-distributed system. Results prove the efficiency of the proposed optimization which can be further implemented for any quasi-distributed sensing application. Fahd Chaoui, Otman Aghzout, Mounia Chakkour, and Mounir El Yakhloufi Copyright © 2016 Fahd Chaoui et al. All rights reserved. Noise Parameter Analysis of SiGe HBTs for Different Sizes in the Breakdown Region Wed, 12 Oct 2016 06:44:41 +0000 Noise parameters of silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) for different sizes are investigated in the breakdown region for the first time. When the emitter length of SiGe HBTs shortens, minimum noise figure at breakdown decreases. In addition, narrower emitter width also decreases noise figure of SiGe HBTs in the avalanche region. Reduction of noise performance for smaller emitter length and width of SiGe HBTs at breakdown resulted from the lower noise spectral density resulting from the breakdown mechanism. Good agreement between experimental and simulated noise performance at breakdown is achieved for different sized SiGe HBTs. The presented analysis can benefit the RF circuits operating in the breakdown region. Chie-In Lee, Yan-Ting Lin, and Wei-Cheng Lin Copyright © 2016 Chie-In Lee et al. All rights reserved. Considerations of Physical Design and Implementation for 5 MHz-100 W LLC Resonant DC-DC Converters Thu, 29 Sep 2016 07:01:15 +0000 Recently, high power-density, high power-efficiency, and wide regulation range isolated DC-DC converters have been required. This paper presents considerations of physical design and implementation for wide regulation range MHz-level LLC resonant DC-DC converters. The circuit parameters are designed with 3–5 MHz-level switching frequency. Also, the physical parameters and the size of the planar transformer are optimized by using derived equations and finite element method (FEM) with Maxwell 3D. Some experiments are done with prototype LLC resonant DC-DC converter using gallium nitride high electron mobility transistors (GaN-HEMTs); the input voltage is 42–53 V, the reference output voltage is 12 V, the load current is 8 A, the maximum switching frequency is about 5 MHz, the total volume of the circuit is 4.1 cm3, and the power density of the prototype converter is 24.4 W/cc. Akinori Hariya, Ken Matsuura, Hiroshige Yanagi, Satoshi Tomioka, Yoichi Ishizuka, and Tamotsu Ninomiya Copyright © 2016 Akinori Hariya et al. All rights reserved. A Structural Based Thermal Model Description for Vertical SiC Power MOSFETs under Fault Conditions Wed, 21 Sep 2016 09:18:42 +0000 The accurate prediction of the SiC MOSFET withstanding time for single fault events greatly influences the requirements for device protection circuits for these devices in power converter applications, like voltage source inverters or power electronic transformers. For this reason, a thermal model, based on the structural design and the physical dimensions of the chip as well as material properties of 4H-SiC, is proposed. This article gives a general description of the thermal behaviour of vertical SiC MOSFET under various driving and boundary conditions in case of a short-circuit event. The thermal model substitutes destructive tests of a device for an individual set of boundary conditions of an occurring fault event. The validity of the analytically parametrised thermal model is verified by experimental short-circuit tests of state-of-the-art vertical SiC MOSFETs for a set of various boundary conditions. The investigated thermal model can furthermore be used to standardise different gate-oxide degradation values from the literature for means of lifetime prediction of the gate oxide for an individual application under repetitive occurring fault or overload conditions. These manufacturer specific reported values measured with no standardised testing procedures can be translated into a maximum junction temperature, which is repeatedly reached. The thermal model therefore provides a unifying parameter for the gate-oxide lifetime calculation for an individual chip and application. Andreas Maerz, Teresa Bertelshofer, and Mark-M. Bakran Copyright © 2016 Andreas Maerz et al. All rights reserved. Design of High-Voltage Switch-Mode Power Amplifier Based on Digital-Controlled Hybrid Multilevel Converter Tue, 20 Sep 2016 14:26:26 +0000 Compared with conventional Class-A, Class-B, and Class-AB amplifiers, Class-D amplifier, also known as switching amplifier, employs pulse width modulation (PWM) technology and solid-state switching devices, capable of achieving much higher efficiency. However, PWM-based switching amplifier is usually designed for low-voltage application, offering a maximum output voltage of several hundred Volts. Therefore, a step-up transformer is indispensably adopted in PWM-based Class-D amplifier to produce high-voltage output. In this paper, a switching amplifier without step-up transformer is developed based on digital pulse step modulation (PSM) and hybrid multilevel converter. Under the control of input signal, cascaded power converters with separate DC sources operate in PSM switch mode to directly generate high-voltage and high-power output. The relevant topological structure, operating principle, and design scheme are introduced. Finally, a prototype system is built, which can provide power up to 1400 Watts and peak voltage up to ±1700 Volts. And the performance, including efficiency, linearity, and distortion, is evaluated by experimental tests. Yanbin Hou, Wanrong Sun, Aifeng Ren, and Shuming Liu Copyright © 2016 Yanbin Hou et al. All rights reserved. The Design and Life Test of a Multifunction Power Amplifier for Space Application Wed, 17 Aug 2016 12:02:58 +0000 A new multifunction power amplifier (MFPA) is designed and fabricated for the application of point-to-point K-Band backhaul TR module. A DC temperature life test was performed to model the up-limit temperature effect of the designed MFPA under space application. After 240 hours of 100°C life test, the test results illustrate that the designed MFPA has only slight power degradation at the saturation region without change of the linear gain. The general performance of the designed MFPA satisfies the requirement of the application scenario. Xiuqin Xu, Hui Xu, Yongheng Shang, Zhiyu Wang, Yang Wang, Liping Wang, Hao Luo, Zhengliang Huang, and Faxin Yu Copyright © 2016 Xiuqin Xu et al. All rights reserved. Analysis of Random Variation in Subthreshold FGMOSFET Thu, 28 Jul 2016 06:06:53 +0000 The analysis of random variation in the performance of Floating Gate Metal Oxide Semiconductor Field Effect Transistor (FGMOSFET) which is an often cited semiconductor based electronic device, operated in the subthreshold region defined in terms of its drain current (), has been proposed in this research. is of interest because it is directly measurable and can be the basis for determining the others. All related manufacturing process induced device level random variations, their statistical correlations, and low voltage/low power operating condition have been taken into account. The analysis result has been found to be very accurate since it can fit the nanometer level SPICE BSIM4 based reference with very high accuracy. By using such result, the strategies for minimizing variation in can be found and the analysis of variation in the circuit level parameter of any subthreshold FGMOSFET based circuit can be performed. So, the result of this research has been found to be beneficial to the variability aware design of subthreshold FGMOSFET based circuit. Rawid Banchuin Copyright © 2016 Rawid Banchuin. All rights reserved.