Review Article
Formal ESL Synthesis for Control-Intensive Applications
Table 2
Area and timing statistics from UMC 65 nm technology implementation.
| Area/time statistic | Massively parallel, initial schedule | Massively parallel, PARCS schedule | FSM + datapath, initial schedule | FSM + datapath, PARCS schedule |
| Area in square nm | 117486 | 114579 | 111025 | 107242 | Equivalent number of NAND2 gates | 91876 | 89515 | 86738 | 83783 | Achievable clock period | 2 ns | 2 ns | 2 ns | 2 ns | Achievable clock frequency | 500 MHz | 500 MHz | 500 MHz | 500 MHz |
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