Table of Contents
Chinese Journal of Engineering
Volume 2014, Article ID 167184, 7 pages
Research Article

Area Efficient Implementation of MTI Processing Module on a Reconfigurable Platform

National University of Sciences and Technology (NUST), Pakistan Navy Engineering College, Karachi 75350, Pakistan

Received 21 October 2013; Accepted 10 November 2013; Published 12 January 2014

Academic Editors: Z. Gu, C.-Y. Sun, and L. Tan

Copyright © 2014 Munaza Yousuf et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents an area efficient Field Programmable Gate Array (FPGA) based digital design of a processing module for MTI radar. Signal contaminated with noise and clutter is modelled to test the efficacy of the design algorithms. For flexibility of design and to achieve optimized results, we have combined the high-level utility of MATLAB with the flexibility and optimization on FPGA for this implementation. Two- and three-pulse cancellers are chosen for design due to its simplicity in both concept and implementation. The results obtained are efficient in terms of enhanced throughput per Slice (TPA) of 1.146, that is, occupying fewer area resources on hardware while achieving optimized speed. The outcomes show that this design of MTI radar processor has many advantages, such as high processing precision, strong processing ability, real time, and low cost. All these advantages greatly contribute to the design requirements and make it appropriate for the application of high-speed signal processing.