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Volume 2017, Article ID 7863095, 15 pages
Research Article

CMOS Realization of All-Positive Pinched Hysteresis Loops

1Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada T2N 1N4
2Department of Electrical and Computer Engineering, University of Sharjah, Sharjah, UAE
3Nanoelectronics Integrated Systems Center (NISC), Nile University, Giza 12588, Egypt
4Physics Department, Electronics Laboratory, University of Patras, Rio, 26504 Patras, Greece

Correspondence should be addressed to B. J. Maundy; ac.yraglacu@ydnuamb

Received 21 March 2017; Accepted 20 June 2017; Published 6 August 2017

Academic Editor: Jesus M. Munoz-Pacheco

Copyright © 2017 B. J. Maundy et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory.