CMOS Realization of All-Positive Pinched Hysteresis Loops
Figure 3
Matlab simulation of the I-V characteristics of Figures 1(a) and 1(b) as given by (8) and (9), respectively. (a) , with . (b) , with . (c) , with and V. (d) , with , V, and V and V for Figures 1(a) and 1(b), respectively.
