Research Article

Evidence of Exponential Speed-Up in the Solution of Hard Optimization Problems

Figure 1

Example of the mapping between a Boolean satisfiability formula in conjunctive normal form and a Boolean circuit made of multiterminal OR and NOT gates. Each clause of the SAT formula is mapped into an OR with as many terminals as the literals in the clause (the satisfiability of this multiterminal OR requires that at least one terminal has a truth value of 1). The global optimum of the SAT formula, that is, the maximum number of satisfied clauses, corresponds to the maximum number of OR gates with output one. This Boolean circuit is then transformed into a self-organizing logic circuit by substituting each standard Boolean gate with a self-organizing logic gate [12], and each OR output is fed with a DC voltage generator representing the logic value of 1.