A New 4D Piecewise Linear Multiscroll Chaotic System with Multistability and Its FPGA-Based Implementation

Table 2

Hardware resources required to implement the proposed multiscroll chaotic system.

Terms	Resource consumptions
Logic elements	2303/10320 (22%)
Registers	1816/10320 (18%)
RAMs implement bits	100352/423936 (24%)
Multipliers elements	0/46 (0%)
PLLs	0/2 (0%)
Throughput (Mbits/s)	100
Clock cycles by iteration	16
Latency (ns)	320