Microcontroller Based Less Switches Topology and Digital Gating Technique for Single-Phase Five-Level Inverter

Table 1

Diode-clamped five-level inverter voltage levels and their switching states [2].

Output 𝑉ao	Switch state
	𝑆a1	𝑆a2	𝑆a3	𝑆a4	𝑆a′1	𝑆a′2	𝑆a′3	𝑆a′4
𝑉5=𝑉dc/2	1	1	1	1	0	0	0	0
𝑉4=𝑉dc/4	0	1	1	1	1	0	0	0
𝑉3=0	0	0	1	1	1	1	0	0
𝑉2=−𝑉dc/4	0	0	0	1	1	1	1	0
𝑉1=−𝑉dc/2	0	0	0	0	1	1	1	1