Microcontroller Based Less Switches Topology and Digital Gating Technique for Single-Phase Five-Level Inverter

Table 2

Switching states for capacitor clamped five-level inverter.

Output voltage	𝑆a1	𝑆a2	𝑆a3	𝑆a4	𝑆a′1	𝑆a′2	𝑆a′3	𝑆a′4
𝑉dc/2	1	1	1	1	0	0	0	0
𝑉dc/4	1	1	1	0	1	0	0	0
0	1	1	0	0	1	1	0	0
−𝑉dc/4	1	0	0	0	1	1	1	0
−𝑉dc/2	0	0	0	0	1	1	1	1