An FPGA-Based PID Controller Design for Chaos Synchronization by Evolutionary Programming

Figure 4

Time responses using the EP-based PID controller. (a) 𝑥_𝑚1versus𝑥_𝑠1. (b) 𝑥_𝑚2versus𝑥_𝑠2. (c) 𝑥_𝑚3versus𝑥_𝑠3. (d) The error states 𝑒₁,𝑒₂,𝑒₃. (e) The control input. (The control 𝑢(𝑡) is activated at 𝑡=20 sec.).

(a)

(b)

(c)

(d)

(e)